s@gcc.gnu.org>>
Cc: Kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2
mailto:pan2...@intel.com>>; Wang, Yanzhang
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic
API
+DEF_RVV_WEXTF_OPS (vfloat32mf2_t, RVV_REQ
Thanks, make sense, will update V2 for this.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, June 5, 2023 3:30 PM
To: Li, Pan2 ; gcc-patches
Cc: Kito.cheng ; Li, Pan2 ; Wang,
Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic
API
+DEF_RVV_WEXTF_OPS
-06-05 14:50
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH floating-point. Aka
SEW=16 for below instructions:
vfadd vfsub vfr
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH floating-point. Aka
SEW=16 for below instructions:
vfadd vfsub vfrsub vfwadd vfwsub
vfmul vfdiv vfrdiv vfwmul
vfmacc vfnmacc vfmsac vfnmsac vfmadd
vfnmadd vfmsub vfnmsub vfwmacc vfwnmacc vfwmsac vfwnmsac
vfsqrt vfrsqrt7 vfrec7
vfmin
