Re: [PATCH v1 0/6] Add Loongson SX/ASX instruction support to LoongArch target.

2023-07-06 Thread Chenghui Pan
No, vld/vst can't guaranteed to be atomic in this condition. Seems we can't implement this on LoongArch for now. On 2023/7/5 20:57, Xi Ruoyao wrote: A question: is vld/vst guaranteed to be atomic if the accessed address is aligned? If true we can use them to implement lock-free 128-bit atomic

Re: [PATCH v1 0/6] Add Loongson SX/ASX instruction support to LoongArch target.

2023-07-05 Thread Xi Ruoyao via Gcc-patches
A question: is vld/vst guaranteed to be atomic if the accessed address is aligned? If true we can use them to implement lock-free 128-bit atomic load and store. See https://gcc.gnu.org/bugzilla/PR104688 for the background, and some people really hate using a lock for atomics. On Fri, 2023-06-30

Re: [PATCH v1 0/6] Add Loongson SX/ASX instruction support to LoongArch target.

2023-06-30 Thread Xi Ruoyao via Gcc-patches
On Fri, 2023-06-30 at 10:16 +0800, Chenghui Pan wrote: > These patches add the Loongson SX/ASX instruction support to the > LoongArch > target, and can be utilized by using the new "-mlsx" and > "-mlasx" option. > > Patches are bootstrapped and tested on loongarch64-linux-gnu target. > > Lulu

[PATCH v1 0/6] Add Loongson SX/ASX instruction support to LoongArch target.

2023-06-29 Thread Chenghui Pan
These patches add the Loongson SX/ASX instruction support to the LoongArch target, and can be utilized by using the new "-mlsx" and "-mlasx" option. Patches are bootstrapped and tested on loongarch64-linux-gnu target. Lulu Cheng (6): LoongArch: Added Loongson SX vector directive compilation