mailto:kito.ch...@gmail.com>;
jeffreyalaw<mailto:jeffreya...@gmail.com>;
rdapp.gcc<mailto:rdapp@gmail.com>; Pan Li<mailto:pan2...@intel.com>
Subject: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
From: Pan Li mailto:pan2...@intel.com>>
After
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
From: Pan Li
After the middle-end support the form 3 of unsigned
From: Pan Li
After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 3 of unsigned .SAT_SUB.
Form 3:
#define SAT_SUB_U_3(T) \
T sat_sub_u_3_##T (T x, T y) \
{ \
return x > y ? x - y : 0; \
