Re: [PATCH v2] RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU

2022-11-28 Thread Maciej W. Rozycki
On Mon, 28 Nov 2022, Jeff Law wrote: > > Given the false negatives how about getting a bit stricter and also > > checking there's nothing following the XORI instruction, like here? > > > > It might be an overkill to have a check both for the sequence and for the > > absence of ANDI or SEXT.W

Re: [PATCH v2] RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU

2022-11-28 Thread Jeff Law via Gcc-patches
On 11/28/22 10:44, Maciej W. Rozycki wrote: Your patch is probably still useful.  I think Kito's only concern was to make sure we don't have the ANDI instruction in addition to not having the SEXT instruction.  So still approved for trunk, just update the testcases to make sure we don't hav

[PATCH v2] RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU

2022-11-28 Thread Maciej W. Rozycki
We produce inefficient code for some synthesized SImode conditional set operations (i.e. ones that are not directly implemented in hardware) on RV64. For example a piece of C code like this: int sleu (unsigned int x, unsigned int y) { return x <= y; } gets compiled (at `-O2') to this: sleu: