>> When you say other variants are still to be implemented
>> does that also include variants for zbb with min/max
>> or zicond?
>
> No, I mean some other forms like branch need the improvement from the
> middle end(aka widen_mul).
Ah, I see, thanks. Those can save one instruction and we want th
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Subject: Re: [PATCH v2] RISC-V: Implement .SAT_SUB for unsigned scalar int
Hi Pan,
> + /* Step-2: lt = x < y */
> + riscv_emit_binary (LTU, pmode_lt, pmode_x, pmode_y);
> +
> + /* Step-3: lt = -lt */
> + riscv_emit_unary (NEG, pmode_lt, p
Hi Pan,
> + /* Step-2: lt = x < y */
> + riscv_emit_binary (LTU, pmode_lt, pmode_x, pmode_y);
> +
> + /* Step-3: lt = -lt */
> + riscv_emit_unary (NEG, pmode_lt, pmode_lt);
> +
> + /* Step-4: lt = ~lt */
> + riscv_emit_unary (NOT, pmode_lt, pmode_lt);
Can we replace step 3 and 4 with sub
From: Pan Li
As the middle support of .SAT_SUB committed, implement the unsigned
scalar int of .SAT_SUB for the riscv backend. Consider below example
code:
T __attribute__((noinline))\
sat_u_sub_##T##_fmt_1 (T x, T y) \
{ \
return (x - y) & (-(T)(x
