On 10/27/22 22:23, Xi Ruoyao via Gcc-patches wrote:
On Thu, 2022-10-27 at 17:44 -0700, Palmer Dabbelt wrote:
though I don't have an opinion on whether libitm should be taking ports
to new targets, I'd never even heard of it before.
I asked this question to myself when I reviewed LoongArch lib
On Thu, 2022-10-27 at 17:44 -0700, Palmer Dabbelt wrote:
> though I don't have an opinion on whether libitm should be taking ports
> to new targets, I'd never even heard of it before.
I asked this question to myself when I reviewed LoongArch libitm port.
But I remember one maintainer of Deepin (
On Thu, 27 Oct 2022 16:05:19 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
>
> On 10/27/22 06:49, Xiongchuan Tan via Gcc-patches wrote:
>> libitm/ChangeLog:
>>
>> * configure.tgt: Add riscv support.
>> * config/riscv/asm.h: New file.
>> * config/riscv/sjlj.S: New file.
>>
On 10/27/22 06:49, Xiongchuan Tan via Gcc-patches wrote:
libitm/ChangeLog:
* configure.tgt: Add riscv support.
* config/riscv/asm.h: New file.
* config/riscv/sjlj.S: New file.
* config/riscv/target.h: New file.
---
v2: Change HW_CACHELINE_SIZE to 64 (in acco
libitm/ChangeLog:
* configure.tgt: Add riscv support.
* config/riscv/asm.h: New file.
* config/riscv/sjlj.S: New file.
* config/riscv/target.h: New file.
---
v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see
https://github.com/riscv/riscv-
