Re: [PATCH v2] RISC-V: Libitm add RISC-V support.

2022-10-28 Thread Jeff Law via Gcc-patches
On 10/27/22 22:23, Xi Ruoyao via Gcc-patches wrote: On Thu, 2022-10-27 at 17:44 -0700, Palmer Dabbelt wrote: though I don't have an opinion on whether libitm should be taking ports to new targets, I'd never even heard of it before. I asked this question to myself when I reviewed LoongArch

Re: [PATCH v2] RISC-V: Libitm add RISC-V support.

2022-10-27 Thread Xi Ruoyao via Gcc-patches
On Thu, 2022-10-27 at 17:44 -0700, Palmer Dabbelt wrote: > though I don't have an opinion on whether libitm should be taking ports > to new targets, I'd never even heard of it before. I asked this question to myself when I reviewed LoongArch libitm port. But I remember one maintainer of Deepin

Re: [PATCH v2] RISC-V: Libitm add RISC-V support.

2022-10-27 Thread Palmer Dabbelt
On Thu, 27 Oct 2022 16:05:19 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > > On 10/27/22 06:49, Xiongchuan Tan via Gcc-patches wrote: >> libitm/ChangeLog: >> >> * configure.tgt: Add riscv support. >> * config/riscv/asm.h: New file. >> * config/riscv/sjlj.S: New file. >>

Re: [PATCH v2] RISC-V: Libitm add RISC-V support.

2022-10-27 Thread Jeff Law via Gcc-patches
On 10/27/22 06:49, Xiongchuan Tan via Gcc-patches wrote: libitm/ChangeLog: * configure.tgt: Add riscv support. * config/riscv/asm.h: New file. * config/riscv/sjlj.S: New file. * config/riscv/target.h: New file. --- v2: Change HW_CACHELINE_SIZE to 64 (in

[PATCH v2] RISC-V: Libitm add RISC-V support.

2022-10-27 Thread Xiongchuan Tan via Gcc-patches
libitm/ChangeLog: * configure.tgt: Add riscv support. * config/riscv/asm.h: New file. * config/riscv/sjlj.S: New file. * config/riscv/target.h: New file. --- v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see