Re: [PATCH v3] [aarch64] Correct the maximum shift amount for shifted operands.

On Wed, Nov 28, 2018 at 07:08:02AM -0600, Philipp Tomsich wrote: > > > On 28.11.2018, at 13:10, Richard Earnshaw (lists) > mailto:richard.earns...@arm.com>> wrote: > > On 26/11/2018 19:50, Christoph Muellner wrote: > The aarch64 ISA specification allows a left shift amount to be applied > after

Re: [PATCH v3] [aarch64] Correct the maximum shift amount for shifted operands.

> On 28.11.2018, at 13:10, Richard Earnshaw (lists) > wrote: > > On 26/11/2018 19:50, Christoph Muellner wrote: >> The aarch64 ISA specification allows a left shift amount to be applied >> after extension in the range of 0 to 4 (encoded in the imm3 field). >> >> This is true for at least the

Re: [PATCH v3] [aarch64] Correct the maximum shift amount for shifted operands.

On 26/11/2018 19:50, Christoph Muellner wrote: > The aarch64 ISA specification allows a left shift amount to be applied > after extension in the range of 0 to 4 (encoded in the imm3 field). > > This is true for at least the following instructions: > > * ADD (extend register) > * ADDS (extended

Re: [PATCH v3] [aarch64] Correct the maximum shift amount for shifted operands.

> On 27.11.2018, at 14:04, Sam Tebbs wrote: > > > On 11/26/18 7:50 PM, Christoph Muellner wrote: >> The aarch64 ISA specification allows a left shift amount to be applied >> after extension in the range of 0 to 4 (encoded in the imm3 field). >> >> This is true for at least the following instr

Re: [PATCH v3] [aarch64] Correct the maximum shift amount for shifted operands.

Sam, > On 27.11.2018, at 14:06, Sam Tebbs wrote: > > > On 11/26/18 7:50 PM, Christoph Muellner wrote: >> The aarch64 ISA specification allows a left shift amount to be applied >> after extension in the range of 0 to 4 (encoded in the imm3 field). >> >> This is true for at least the following i

Re: [PATCH v3] [aarch64] Correct the maximum shift amount for shifted operands.

On 11/26/18 7:50 PM, Christoph Muellner wrote: > The aarch64 ISA specification allows a left shift amount to be applied > after extension in the range of 0 to 4 (encoded in the imm3 field). > > This is true for at least the following instructions: > > * ADD (extend register) > * ADDS (extended reg

[PATCH v3] [aarch64] Correct the maximum shift amount for shifted operands.

The aarch64 ISA specification allows a left shift amount to be applied after extension in the range of 0 to 4 (encoded in the imm3 field). This is true for at least the following instructions: * ADD (extend register) * ADDS (extended register) * SUB (extended register) The result of this patc