Re: [PATCH v3] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-06-27 Thread Alexandre Oliva
On Jun 26, 2024, Richard Sandiford wrote: > Alexandre Oliva writes: >> On Jun 25, 2024, Richard Sandiford wrote: >> Richard (Sandiford), do you happen to recall why the IRC conversation mentioned in the PR trail decided to drop it entirely, even for signed types? >> >>> In the

Re: [PATCH v3] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-06-26 Thread Richard Sandiford
Alexandre Oliva writes: > On Jun 25, 2024, Richard Sandiford wrote: > >>> Richard (Sandiford), do you happen to recall why the IRC conversation >>> mentioned in the PR trail decided to drop it entirely, even for signed >>> types? > >> In the PR, the original shift was 32768 >> x (x >= 16) on

Re: [PATCH v3] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-06-25 Thread Alexandre Oliva
On Jun 25, 2024, Richard Sandiford wrote: >> Richard (Sandiford), do you happen to recall why the IRC conversation >> mentioned in the PR trail decided to drop it entirely, even for signed >> types? > In the PR, the original shift was 32768 >> x (x >= 16) on ints, which the > vectoriser was

Re: [PATCH v3] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-06-25 Thread Richard Sandiford
Alexandre Oliva writes: > On Jun 24, 2024, "Richard Earnshaw (lists)" wrote: > >> A signed shift right on a 16-bit vector element by 15 would still >> yield -1 > > Yeah. Indeed, ISTM that we *could* have retained the clamping > transformation for *signed* shifts, since the clamping would only

Re: [PATCH v3] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-06-24 Thread Alexandre Oliva
On Jun 24, 2024, "Richard Earnshaw (lists)" wrote: > A signed shift right on a 16-bit vector element by 15 would still > yield -1 Yeah. Indeed, ISTM that we *could* have retained the clamping transformation for *signed* shifts, since the clamping would only make a difference in case of

Re: [PATCH v3] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-06-24 Thread Richard Earnshaw (lists)
On 24/06/2024 12:35, Alexandre Oliva wrote: > On Jun 21, 2024, Christophe Lyon wrote: > >>> How about mentioning Christophe's simplification in the commit log? > >> For the avoidance of doubt: it's OK for me (but you don't need to >> mention my name in fact ;-) > > Needing or not, I added it

Re: [PATCH v3] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-06-24 Thread Alexandre Oliva
On Jun 21, 2024, Christophe Lyon wrote: >> How about mentioning Christophe's simplification in the commit log? > For the avoidance of doubt: it's OK for me (but you don't need to > mention my name in fact ;-) Needing or not, I added it ;-) >> > be accepted. (int16_t)32768 >> (int16_t)16 must

Re: [PATCH v3] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-06-21 Thread Christophe Lyon
On Fri, 21 Jun 2024 at 12:14, Richard Earnshaw (lists) wrote: > > On 21/06/2024 08:57, Alexandre Oliva wrote: > > On Jun 20, 2024, Christophe Lyon wrote: > > > >> Maybe using > >> if ((unsigned)b[i] >= BITS) \ > >> would be clearer? > > > > Heh. Why make it simpler if we can make it unreadable,

Re: [PATCH v3] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-06-21 Thread Richard Earnshaw (lists)
On 21/06/2024 08:57, Alexandre Oliva wrote: > On Jun 20, 2024, Christophe Lyon wrote: > >> Maybe using >> if ((unsigned)b[i] >= BITS) \ >> would be clearer? > > Heh. Why make it simpler if we can make it unreadable, right? :-D > > Thanks, here's another version I've just retested on

[PATCH v3] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

2024-06-21 Thread Alexandre Oliva
On Jun 20, 2024, Christophe Lyon wrote: > Maybe using > if ((unsigned)b[i] >= BITS) \ > would be clearer? Heh. Why make it simpler if we can make it unreadable, right? :-D Thanks, here's another version I've just retested on x-arm-eabi. Ok? I'm not sure how to credit your suggestion. It's