Re: [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

2023-12-21 Thread Kito Cheng
Why not just check the prefix is 'v'? I don't think xtheadvector able to work with other vector stuffs like vector crypto or any other new vector stuffs, then we don't need extra attribute. On Thu, Dec 21, 2023 at 12:42 PM Jeff Law wrote: > > > > On 12/20/23 15:48, 钟居哲 wrote: > > >> So rather

Re: [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

2023-12-20 Thread Jeff Law
On 12/20/23 15:48, 钟居哲 wrote: >> So rather than looking at the mode, would it make more sense to have an attribute (or re-use an existing attribute) to identify which opcodes are going to need prefixing?  We've got access to the INSN via current_output_insn.  So we can lookup attributes

Re: Re: [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

2023-12-20 Thread 钟居哲
>> So rather than looking at the mode, would it make more sense to have an >> attribute (or re-use an existing attribute) to identify which opcodes >> are going to need prefixing? We've got access to the INSN via >> current_output_insn. So we can lookup attributes trivially. Yes, I totally

Re: [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

2023-12-20 Thread Jeff Law
On 12/20/23 05:32, Jun Sha (Joshua) wrote: This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): New function. * config/riscv/riscv.cc

[PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

2023-12-20 Thread Jun Sha (Joshua)
This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): New function. * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. *