These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-14 Patrick O'Neill <patr...@rivosinc.com>
* amo-table-a-6-amo-add-1.c: New test.
* amo-table-a-6-amo-add-2.c: Likewise.
* amo-table-a-6-amo-add-3.c: Likewise.
* amo-table-a-6-amo-add-4.c: Likewise.
* amo-table-a-6-amo-add-5.c: Likewise.
* amo-table-a-6-compare-exchange-1.c: Likewise.
* amo-table-a-6-compare-exchange-2.c: Likewise.
* amo-table-a-6-compare-exchange-3.c: Likewise.
* amo-table-a-6-compare-exchange-4.c: Likewise.
* amo-table-a-6-compare-exchange-5.c: Likewise.
* amo-table-a-6-compare-exchange-6.c: Likewise.
* amo-table-a-6-compare-exchange-7.c: Likewise.
* amo-table-a-6-fence-1.c: Likewise.
* amo-table-a-6-fence-2.c: Likewise.
* amo-table-a-6-fence-3.c: Likewise.
* amo-table-a-6-fence-4.c: Likewise.
* amo-table-a-6-fence-5.c: Likewise.
* amo-table-a-6-load-1.c: Likewise.
* amo-table-a-6-load-2.c: Likewise.
* amo-table-a-6-load-3.c: Likewise.
* amo-table-a-6-store-1.c: Likewise.
* amo-table-a-6-store-2.c: Likewise.
* amo-table-a-6-store-compat-3.c: Likewise.
Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>
---
v3 Changelog:
* Consolidate existing tests in this patch
* Add new tests for store/load/amoadd
---
v4 Changelog:
* Add additional compare-exchange testcases
* Update assertions to use scan-assembler-times for fences
---
.../gcc.target/riscv/amo-table-a-6-amo-add-1.c | 8 ++++++++
.../gcc.target/riscv/amo-table-a-6-amo-add-2.c | 8 ++++++++
.../gcc.target/riscv/amo-table-a-6-amo-add-3.c | 8 ++++++++
.../gcc.target/riscv/amo-table-a-6-amo-add-4.c | 8 ++++++++
.../gcc.target/riscv/amo-table-a-6-amo-add-5.c | 8 ++++++++
.../riscv/amo-table-a-6-compare-exchange-1.c | 10 ++++++++++
.../riscv/amo-table-a-6-compare-exchange-2.c | 10 ++++++++++
.../riscv/amo-table-a-6-compare-exchange-3.c | 10 ++++++++++
.../riscv/amo-table-a-6-compare-exchange-4.c | 10 ++++++++++
.../riscv/amo-table-a-6-compare-exchange-5.c | 10 ++++++++++
.../riscv/amo-table-a-6-compare-exchange-6.c | 11 +++++++++++
.../riscv/amo-table-a-6-compare-exchange-7.c | 10 ++++++++++
.../gcc.target/riscv/amo-table-a-6-fence-1.c | 8 ++++++++
.../gcc.target/riscv/amo-table-a-6-fence-2.c | 10 ++++++++++
.../gcc.target/riscv/amo-table-a-6-fence-3.c | 10 ++++++++++
.../gcc.target/riscv/amo-table-a-6-fence-4.c | 10 ++++++++++
.../gcc.target/riscv/amo-table-a-6-fence-5.c | 10 ++++++++++
gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c | 11 +++++++++++
gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c | 11 +++++++++++
.../gcc.target/riscv/amo-table-a-6-store-1.c | 9 +++++++++
.../gcc.target/riscv/amo-table-a-6-store-2.c | 11 +++++++++++
.../gcc.target/riscv/amo-table-a-6-store-compat-3.c | 11 +++++++++++
23 files changed, 221 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
new file mode 100644
index 00000000000..ae7e407befc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "amoadd.w\t" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
new file mode 100644
index 00000000000..60d84f32481
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "amoadd.w.aq\t" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
new file mode 100644
index 00000000000..a97231e4e73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "amoadd.w.rl\t" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
new file mode 100644
index 00000000000..3c843afdd5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
new file mode 100644
index 00000000000..3434229f5e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
new file mode 100644
index 00000000000..a9141cde48f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELAXED,
__ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
new file mode 100644
index 00000000000..b1ebb20e2f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_CONSUME,
__ATOMIC_CONSUME);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
new file mode 100644
index 00000000000..47d8d02f7e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_ACQUIRE,
__ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
new file mode 100644
index 00000000000..af6e1d69c75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE,
__ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
new file mode 100644
index 00000000000..ceb5660b6af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST,
__ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
new file mode 100644
index 00000000000..7b012fb1288
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* Mixed mappings need to be unioned. */
+/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE,
__ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
new file mode 100644
index 00000000000..5adec6f7a19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST,
__ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
new file mode 100644
index 00000000000..b8c28013ef3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-not "fence\t" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+int main() {
+ __atomic_thread_fence(__ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
new file mode 100644
index 00000000000..117f9036e39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */
+/* { dg-final { scan-assembler-not "fence\trw,w" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+
+int main() {
+ __atomic_thread_fence(__ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
new file mode 100644
index 00000000000..4b6dd7a9aa7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */
+/* { dg-final { scan-assembler-not "fence\tr,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+
+int main() {
+ __atomic_thread_fence(__ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
new file mode 100644
index 00000000000..d40d3bc37db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-times "fence.tso" 1 } } */
+/* { dg-final { scan-assembler-not "fence\trw,w" } } */
+/* { dg-final { scan-assembler-not "fence\tr,rw" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+
+int main() {
+ __atomic_thread_fence(__ATOMIC_ACQ_REL);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
new file mode 100644
index 00000000000..71f76c27789
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+/* { dg-final { scan-assembler-not "fence\trw,w" } } */
+/* { dg-final { scan-assembler-not "fence\tr,rw" } } */
+
+int main() {
+ __atomic_thread_fence(__ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
new file mode 100644
index 00000000000..8278198072e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* Verify that load mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-not "fence\t" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
new file mode 100644
index 00000000000..84b6cc542ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* Verify that load mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */
+/* { dg-final { scan-assembler-not "fence\trw,w" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
new file mode 100644
index 00000000000..3f15041d117
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* Verify that load mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */
+/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */
+/* { dg-final { scan-assembler-not "fence\trw,w" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
new file mode 100644
index 00000000000..c200bd1d11d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* Verify that store mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-not "fence\t" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
new file mode 100644
index 00000000000..1cf366b5986
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* Verify that store mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */
+/* { dg-final { scan-assembler-not "fence\tr,rw" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
new file mode 100644
index 00000000000..288e1493156
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* Verify that store mapping are compatible with Table A.6 & A.7. */
+/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */
+/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */
+/* { dg-final { scan-assembler-not "fence\tr,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
--
2.25.1
