[PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-11 Thread Jun Sha (Joshua)
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we add an attribute "spec_restriction" to di

Re: [PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-11 Thread juzhe.zh...@rivai.ai
ok. juzhe.zh...@rivai.ai From: Jun Sha (Joshua) Date: 2024-01-12 11:23 To: gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu Subject: [PATCH v6] RISC-V: Fix register overlap issue for some