On Thu, 3 Sep 2020, Alexandre Oliva wrote:
> On Sep 3, 2020, Segher Boessenkool wrote:
> > For instructions that inherently set a condition code register, the
> > @code{compare} operator is always written as the first RTL expression of
> > the @code{parallel} instruction pattern.
>
>
On Sep 4, 2020, Segher Boessenkool wrote:
> Please open a PR? (But see below first.)
I saw the bit below, then filed
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96965
> Btw, we could perhaps try permuting arms in combine itself (not in
> recog)? In combine we know that there are at most 4
On Thu, Sep 03, 2020 at 04:46:43PM -0300, Alexandre Oliva wrote:
> On Sep 3, 2020, Segher Boessenkool wrote:
> > The idea is that none of them will need adjustment. This hook runs
> > before the "none" code will run, and it can just clear all clobbers
> > then.
>
> Uhh... That's not how asm
Hi!
On Thu, Sep 03, 2020 at 04:31:35PM -0300, Alexandre Oliva wrote:
> Except when it doesn't ;-)
Heh. PRs welcome :-)
> Under:
>
> /* If the actions of the earlier insns must be kept
> in addition to substituting them into the latest one,
> we must make a new PARALLEL for the
On Sep 3, 2020, Segher Boessenkool wrote:
> On Thu, Sep 03, 2020 at 02:17:04PM -0300, Alexandre Oliva wrote:
>> On Sep 3, 2020, Segher Boessenkool wrote:
>> > Oh, I meant what was in your patch. From a grep, all of mn10300, nds32,
>> > arm, cris, pdp11, rs6000, i386, visium, aarch64 have
On Sep 3, 2020, Segher Boessenkool wrote:
> On Thu, Sep 03, 2020 at 02:07:24PM -0300, Alexandre Oliva wrote:
>> On Sep 3, 2020, Segher Boessenkool wrote:
>> > On Thu, Sep 03, 2020 at 07:03:53AM -0300, Alexandre Oliva wrote:
>> >> On Sep 2, 2020, Segher Boessenkool wrote:
>> >> >> we might
On Thu, Sep 03, 2020 at 02:17:04PM -0300, Alexandre Oliva wrote:
> On Sep 3, 2020, Segher Boessenkool wrote:
> > Oh, I meant what was in your patch. From a grep, all of mn10300, nds32,
> > arm, cris, pdp11, rs6000, i386, visium, aarch64 have default clobbers.
> > Hrm, what you said was the
On Thu, Sep 03, 2020 at 02:07:24PM -0300, Alexandre Oliva wrote:
> On Sep 3, 2020, Segher Boessenkool wrote:
> > On Thu, Sep 03, 2020 at 07:03:53AM -0300, Alexandre Oliva wrote:
> >> On Sep 2, 2020, Segher Boessenkool wrote:
> >> >> we might succeed, but only if we had a pattern
> >> >> that
On Sep 3, 2020, Segher Boessenkool wrote:
> On Thu, Sep 03, 2020 at 07:03:53AM -0300, Alexandre Oliva wrote:
>> On Sep 2, 2020, Segher Boessenkool wrote:
>> > (And aarch, but not the other targets with default clobbers).
>>
>> And arm. I didn't look very hard for others yet; I wasn't sure
[dropping port maintainers for combine-mostly subthread]
On Sep 3, 2020, Segher Boessenkool wrote:
> On Thu, Sep 03, 2020 at 07:03:53AM -0300, Alexandre Oliva wrote:
>> On Sep 2, 2020, Segher Boessenkool wrote:
>> >> we might succeed, but only if we had a pattern
>> >> that matched
On Thu, Sep 03, 2020 at 07:03:53AM -0300, Alexandre Oliva wrote:
> On Sep 2, 2020, Segher Boessenkool wrote:
> > (And aarch, but not the other targets with default clobbers).
>
> And arm. I didn't look very hard for others yet; I wasn't sure it would
> be worth pursuing any further.
Oh, I
On Sep 2, 2020, Segher Boessenkool wrote:
> Hi!
> On Tue, Sep 01, 2020 at 07:22:57PM -0300, Alexandre Oliva wrote:
>> It's ugly, I know.
> Yeah, it's bloody disgusting :-)
:-)
> (And aarch, but not the other targets with default clobbers).
And arm. I didn't look very hard for others yet; I
Hi!
On Tue, Sep 01, 2020 at 07:22:57PM -0300, Alexandre Oliva wrote:
> This WIP patchlet introduces means for machines that implicitly clobber
> cc flags in asm statements, but that have machinery to output flags
> (namely x86, non-thumb arm and aarch64), to state that the asm statement
> does
This WIP patchlet introduces means for machines that implicitly clobber
cc flags in asm statements, but that have machinery to output flags
(namely x86, non-thumb arm and aarch64), to state that the asm statement
does NOT clobber cc flags. That's accomplished by using "=@ccC" in the
output
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