This patch sets the relevant .rl bits on amo operations. 2022-03-31 Patrick O'Neill <patr...@rivosinc.com>
* riscv.cc (riscv_print_operand): change behavior of %A to include release bits. Signed-off-by: Patrick O'Neill <patr...@rivosinc.com> --- gcc/config/riscv/riscv.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ee756aab694..813e771bec7 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3652,8 +3652,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)) && + riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) fputs (".aq", file); + else if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) + fputs (".rl", file); break; case 'F': -- 2.25.1