On 2/28/23 09:42, Maciej W. Rozycki wrote:
On Mon, 13 Feb 2023, Jeff Law via Gcc-patches wrote:
3. The canaonical conditional-zero-or-value assumes the target can do a
generic SEQ/SNE of two register values. As you know, on RISC-V we have
SEQZ/SNEZ. So we've added another fallback path to
On Mon, 13 Feb 2023, Jeff Law via Gcc-patches wrote:
> 3. The canaonical conditional-zero-or-value assumes the target can do a
> generic SEQ/SNE of two register values. As you know, on RISC-V we have
> SEQZ/SNEZ. So we've added another fallback path to handle that case in
> noce_emit_condzero.
On Mon, Feb 13, 2023 at 10:43 AM Jeff Law wrote:
>
>
>
> On 2/13/23 10:32, Richard Sandiford via Gcc-patches wrote:
> > Andrew Pinski via Gcc-patches writes:
> >> On Fri, Feb 10, 2023 at 2:47 PM Philipp Tomsich
> >> wrote:
> >>>
> >>> Some architectures, as it the case on RISC-V with the propose
On 2/13/23 10:32, Richard Sandiford via Gcc-patches wrote:
Andrew Pinski via Gcc-patches writes:
On Fri, Feb 10, 2023 at 2:47 PM Philipp Tomsich
wrote:
Some architectures, as it the case on RISC-V with the proposed
ZiCondOps and the vendor-defined XVentanaCondOps, define a
conditional-zer
Andrew Pinski via Gcc-patches writes:
> On Fri, Feb 10, 2023 at 2:47 PM Philipp Tomsich
> wrote:
>>
>> Some architectures, as it the case on RISC-V with the proposed
>> ZiCondOps and the vendor-defined XVentanaCondOps, define a
>> conditional-zero instruction that is equivalent to:
>> - the posi
On 2/10/23 15:41, Philipp Tomsich wrote:
Some architectures, as it the case on RISC-V with the proposed
ZiCondOps and the vendor-defined XVentanaCondOps, define a
conditional-zero instruction that is equivalent to:
- the positive form: rd = (rc != 0) ? rs : 0
- the negated form: rd = (r
On Fri, Feb 10, 2023 at 2:47 PM Philipp Tomsich
wrote:
>
> Some architectures, as it the case on RISC-V with the proposed
> ZiCondOps and the vendor-defined XVentanaCondOps, define a
> conditional-zero instruction that is equivalent to:
> - the positive form: rd = (rc != 0) ? rs : 0
> - the neg
Some architectures, as it the case on RISC-V with the proposed
ZiCondOps and the vendor-defined XVentanaCondOps, define a
conditional-zero instruction that is equivalent to:
- the positive form: rd = (rc != 0) ? rs : 0
- the negated form: rd = (rc == 0) ? rs : 0
While noce_try_store_flag_mask
