> Some ISAs have instructions to perform a bitwise AND operation with an
> immediate and compare the result with zero.
Many of them I'd say.
> Is there a good way to fix this? It would seem rather weird to have extra MD
> patterns to match the zero_extract forms explicitly. Maybe teaching the
> a
Hi all,
Some ISAs have instructions to perform a bitwise AND operation with an
immediate and compare
the result with zero. For example, the aarch64 TST instruction.
This is represented naturally in the MD file as:
(define_insn "*and3nr_compare0"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
