ch; jeffreyalaw; christoph.muellner
主题： 回复：回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
Sorry but I'm not quite familiar with the group_overlap framework. Could you
take this pattern as an example to show how to disable an alternative in s
日(星期五) 18:32
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Yeah.
(define_insn "@pre
On 12/22/23 01:07, juzhe.zh...@rivai.ai wrote:
You mean theadvector doesn't want the current RVV1.0 register overlap
magic as follows ?
*
The destination EEW is smaller than the source EEW and the overlap
is in the lowest-numbered part of the source register group (e.g.,
when
ot; "4")
(set (attr "avl_type_idx") (const_int 5))])
You should use an attribute to disable alternative 0 and alternative 1
constraint.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2023-12-22 18:29
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich
-------------------------
发件人：juzhe.zh...@rivai.ai
发送时间：2023年12月22日(星期五) 16:07
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
erlap constraint using attribute, More details
you can learn from
(set_attr "group_overlap"
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2023-12-22 11:33
收件人： 钟居哲; gcc-patches
抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Jeff Law; Christoph
Müllner; jinma; Cooper Qu
主题： 回复：[PATCH
Hi Juzhe,
Thank you for your comprehensive comments.
Classifying theadvector intrinsics into 3 kinds is really important to make our
patchset more organized.
For 1) and 3), I will split out the patches soon and hope they will be merged
quickly.
For 2), according to the differences between vector
