On Fri, Apr 18, 2014 at 2:16 PM, Jan Hubicka wrote:
>> On Fri, Apr 18, 2014 at 12:27 PM, Jan Hubicka wrote:
>> >> What I've observed on power is that LTO alone reduces performance and
>> >> LTO+FDO is not significantly different than FDO alone.
>> > On SPEC2k6?
>> >
>> > This is quite surprising,
> On Fri, Apr 18, 2014 at 12:27 PM, Jan Hubicka wrote:
> >> What I've observed on power is that LTO alone reduces performance and
> >> LTO+FDO is not significantly different than FDO alone.
> > On SPEC2k6?
> >
> > This is quite surprising, for our (well SUSE's) spec testers (AMD64) LTO
> > seems
On Fri, Apr 18, 2014 at 12:51 PM, Jan Hubicka wrote:
>> What I've observed on power is that LTO alone reduces performance and
>> LTO+FDO is not significantly different than FDO alone.
>>
>> I agree that an exact estimate of the register pressure would be a
>> difficult problem. I'm hoping that som
On Fri, Apr 18, 2014 at 12:27 PM, Jan Hubicka wrote:
>> What I've observed on power is that LTO alone reduces performance and
>> LTO+FDO is not significantly different than FDO alone.
> On SPEC2k6?
>
> This is quite surprising, for our (well SUSE's) spec testers (AMD64) LTO seems
> off-noise win o
> What I've observed on power is that LTO alone reduces performance and
> LTO+FDO is not significantly different than FDO alone.
>
> I agree that an exact estimate of the register pressure would be a
> difficult problem. I'm hoping that something that approximates potential
> register pressure dow
> What I've observed on power is that LTO alone reduces performance and
> LTO+FDO is not significantly different than FDO alone.
On SPEC2k6?
This is quite surprising, for our (well SUSE's) spec testers (AMD64) LTO seems
off-noise win on SPEC2k6
http://gcc.opensuse.org/SPEC/CINT/sb-megrez-head-64-2
What I've observed on power is that LTO alone reduces performance and
LTO+FDO is not significantly different than FDO alone.
I agree that an exact estimate of the register pressure would be a
difficult problem. I'm hoping that something that approximates potential
register pressure downstream will
On Fri, 2014-04-18 at 19:26 +0200, Jan Hubicka wrote:
> This is intresting. I sort of planned to add register pressure logic
> but always tought it is somewhat hard to do at GIMPLE level in a way
> that would work for all CPUs.
Yes, this is just meant to try to measure something that is
represent
On Fri, Apr 18, 2014 at 10:26 AM, Jan Hubicka wrote:
> Hello,
>> Honza,
>> Seeing your recent patches relating to inliner heuristics for LTO,
>> I thought I should mention some related work I'm doing.
>>
>> By way of introduction, I've recently joined the IBM LTC's PPC
>> Toolchain team, working
Do you witness similar problems with LTO +FDO?
My concern is it can be tricky to get the register pressure estimate
right. The register pressure problem is created by downstream
components (code motions etc) but only exposed by the inliner. If you
want to get it 'right' (i.e., not exposing the pr
Hello,
> Honza,
> Seeing your recent patches relating to inliner heuristics for LTO,
> I thought I should mention some related work I'm doing.
>
> By way of introduction, I've recently joined the IBM LTC's PPC
> Toolchain team, working on gcc performance.
>
> We have not generally seen good res
Honza,
Seeing your recent patches relating to inliner heuristics for LTO, I
thought I should mention some related work I'm doing.
By way of introduction, I've recently joined the IBM LTC's PPC Toolchain
team, working on gcc performance.
We have not generally seen good results using LTO on
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