Re: Out-of-order update of new_spill_reg_store[]

2012-02-02 Thread Ulrich Weigand
Richard Sandiford wrote: > "Ulrich Weigand" writes: > > Richard Sandiford wrote: > >> Either way, the idea is that new_spill_reg_store[R] is only valid > >> for reload registers R that reach the end of the reload sequence. > >> We really should check that H1 reaches the end before u

Re: Out-of-order update of new_spill_reg_store[]

2012-02-01 Thread Richard Sandiford
Thanks for looking at this. "Ulrich Weigand" writes: > Richard Sandiford wrote: >> Either way, the idea is that new_spill_reg_store[R] is only valid >> for reload registers R that reach the end of the reload sequence. >> We really should check that H1 reaches the end before using >

Re: Out-of-order update of new_spill_reg_store[]

2012-02-01 Thread Ulrich Weigand
Richard Sandiford wrote: > Bernd Schmidt writes: > >> gcc/ > >>* reload1.c (reload_regs_reach_end_p): Replace with... > >>(reload_reg_rtx_reaches_end_p): ...this function. > >>(new_spill_reg_store): Update commentary. > >>(emit_input_reload_insns): Don't clear new_spill_reg_store h

Ping^5: Out-of-order update of new_spill_reg_store[]

2012-02-01 Thread Richard Sandiford
Ping for this reload inheritance patch: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg00266.html or perhaps the original: http://gcc.gnu.org/ml/gcc-patches/2011-10/msg00663.html It fixes some wrong-code regressions in execute/scal-to-vec1.c on mips64-linux-gnu and mips64-elf. Richard

Ping^4: Out-of-order update of new_spill_reg_store[]

2012-01-22 Thread Richard Sandiford
Ping for this reload patch: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg00266.html or perhaps the original: http://gcc.gnu.org/ml/gcc-patches/2011-10/msg00663.html which fixes some wrong-code regressions on mips64-linux-gnu. Richard

Ping^3: Out-of-order update of new_spill_reg_store[]

2012-01-17 Thread Richard Sandiford
Ping for this reload patch: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg00266.html or perhaps the original: http://gcc.gnu.org/ml/gcc-patches/2011-10/msg00663.html which fixes some wrong-code regressions on mips64-linux-gnu. Richard

Ping^2: Out-of-order update of new_spill_reg_store[]

2012-01-02 Thread Richard Sandiford
Ping for this reload patch: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg00266.html or perhaps the original: http://gcc.gnu.org/ml/gcc-patches/2011-10/msg00663.html which fixes some wrong-code regressions on mips64-linux-gnu. Richard

Ping: Out-of-order update of new_spill_reg_store[]

2011-12-17 Thread Richard Sandiford
Ping for this reload patch: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg00266.html or perhaps the original: http://gcc.gnu.org/ml/gcc-patches/2011-10/msg00663.html which fixes some wrong-code regressions on mips64-linux-gnu. Richard

Re: Out-of-order update of new_spill_reg_store[]

2011-12-04 Thread Richard Sandiford
Back to this... Bernd Schmidt writes: >> gcc/ >> * reload1.c (reload_regs_reach_end_p): Replace with... >> (reload_reg_rtx_reaches_end_p): ...this function. >> (new_spill_reg_store): Update commentary. >> (emit_input_reload_insns): Don't clear new_spill_reg_store here. >>

Re: Out-of-order update of new_spill_reg_store[]

2011-10-17 Thread Bernd Schmidt
> gcc/ > * reload1.c (reload_regs_reach_end_p): Replace with... > (reload_reg_rtx_reaches_end_p): ...this function. > (new_spill_reg_store): Update commentary. > (emit_input_reload_insns): Don't clear new_spill_reg_store here. > (emit_output_reload_insns): Check reload

Re: Out-of-order update of new_spill_reg_store[]

2011-10-12 Thread Richard Sandiford
Bernd Schmidt writes: > On 10/11/11 14:35, Richard Sandiford wrote: >> No, reload 1 is inherited by a later instruction. And it's inherited >> correctly, in terms of the register contents being what we expect. >> (Reload 1 is the one that survives to the end of the instruction's >> reload sequenc

Re: Out-of-order update of new_spill_reg_store[]

2011-10-12 Thread Bernd Schmidt
On 10/11/11 14:35, Richard Sandiford wrote: > No, reload 1 is inherited by a later instruction. And it's inherited > correctly, in terms of the register contents being what we expect. > (Reload 1 is the one that survives to the end of the instruction's > reload sequence. Reload 2, in contrast, is

Re: Out-of-order update of new_spill_reg_store[]

2011-10-11 Thread Richard Sandiford
Bernd Schmidt writes: > On 10/09/11 10:01, Richard Sandiford wrote: >> Reload 0: GR_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, >> secondary_reload_p >> reload_reg_rtx: (reg:SI 5 $5) >> Reload 1: reload_out (SI) = (reg:SI 32 $f0 [1655]) >> MD1_REG, RELOAD_FOR_OUTPU

Re: Out-of-order update of new_spill_reg_store[]

2011-10-11 Thread Bernd Schmidt
I'm not completely following this yet, so please bear with me... On 10/09/11 10:01, Richard Sandiford wrote: > Reload 0: GR_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, > secondary_reload_p > reload_reg_rtx: (reg:SI 5 $5) > Reload 1: reload_out (SI) = (reg:SI 32 $f0 [1655])

Out-of-order update of new_spill_reg_store[]

2011-10-09 Thread Richard Sandiford
This patch fixes an ordering problem in reload: the output reloads are emitted in reverse operand order, but new_spill_reg_store[] is updated in forward reload order. This causes problems if the same register is used for two reloads. I saw this hit on mips64-linux-gnu/-mabi=64 as a failure in exe