> -Original Message-
> From: Richard Sandiford
> Sent: 29 April 2019 09:42
> To: Alejandro Martinez Vicente
> Cc: GCC Patches ; nd ; Richard
> Biener
> Subject: Re: [Aarch64][SVE] Dot product support
>
> Alejandro Martinez Vicente writ
Alejandro Martinez Vicente writes:
> @@ -5885,6 +5885,56 @@ is_nonwrapping_integer_induction (stmt_vec_info
> stmt_vinfo, struct loop *loop)
> <= TYPE_PRECISION (lhs_type));
> }
>
> +/* Check if masking can be supported by inserting a condional expression.
conditional
> + CODE is t
lejandro Martinez Vicente
> Cc: GCC Patches ; nd ; Richard
> Biener
> Subject: Re: [Aarch64][SVE] Dot product support
>
> Alejandro Martinez Vicente writes:
> > Hi,
> >
> > This patch does two things. For the general vectorizer, it adds
> > support to per
Alejandro Martinez Vicente writes:
> Hi,
>
> This patch does two things. For the general vectorizer, it adds support to
> perform fully masked reductions over expressions that don't support masking.
> This is achieved by using VEC_COND_EXPR where possible. At the moment this is
> implemented for
