> -----Original Message-----
> From: Gcc-patches <gcc-patches-boun...@gcc.gnu.org> On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 11 December 2020 18:37
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH v3 1/4] arm: Auto-vectorization for MVE: veor
>
> This patch enables MVE veorq instructions for auto-vectorization. MVE
> veorq insns in mve.md are modified to use xor instead of unspec
> expression to support xor<mode>3. The xor<mode>3 expander is added to
> vec-common.md
>
Ok.
Thanks,
Kyrill
> 2020-12-11 Christophe Lyon <christophe.l...@linaro.org>
>
> gcc/
> * config/arm/iterators.md (supf): Remove VEORQ_S and VEORQ_U.
> (VEORQ): Remove.
> * config/arm/mve.md (mve_veorq_u<mode>): New entry for veor
> instruction using expression xor.
> (mve_veorq_s<mode>): New expander.
> (mve_veorq_f<mode>): Use 'xor' code instead of unspec.
> * config/arm/neon.md (xor<mode>3): Renamed into
> xor<mode>3_neon.
> * config/arm/unspecs.md (VEORQ_S, VEORQ_U, VEORQ_F): Remove.
> * config/arm/vec-common.md (xor<mode>3): New expander.
>
> gcc/testsuite/
> * gcc.target/arm/simd/mve-veor.c: Add tests for veor.
> ---
> gcc/config/arm/iterators.md | 3 +-
> gcc/config/arm/mve.md | 22 ++++++----
> gcc/config/arm/neon.md | 2 +-
> gcc/config/arm/unspecs.md | 3 --
> gcc/config/arm/vec-common.md | 7 ++++
> gcc/testsuite/gcc.target/arm/simd/mve-veor.c | 61
> ++++++++++++++++++++++++++++
> 6 files changed, 84 insertions(+), 14 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-veor.c
>
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index 5fcb7af..0195275 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -1237,7 +1237,7 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s")
> (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
> (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
> (VCMPEQQ_S "s") (VCMPEQQ_U "u")
> (VCADDQ_ROT90_U "u")
> (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u")
> (VCMPNEQ_N_S "s")
> - (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
> + (VCMPNEQ_N_U "u")
> (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
> (VHADDQ_U "u") (VHSUBQ_N_S "s")
> (VHSUBQ_N_U "u")
> (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u")
> (VHSUBQ_U "u")
> @@ -1507,7 +1507,6 @@ (define_int_iterator VCADDQ_ROT90
> [VCADDQ_ROT90_U VCADDQ_ROT90_S])
> (define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
> (define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
> (define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
> -(define_int_iterator VEORQ [VEORQ_U VEORQ_S])
> (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
> (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
> (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 4b2e46a..10512ad 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -1207,17 +1207,24 @@ (define_insn "mve_vcmpneq_n_<supf><mode>"
> ;;
> ;; [veorq_u, veorq_s])
> ;;
> -(define_insn "mve_veorq_<supf><mode>"
> +(define_insn "mve_veorq_u<mode>"
> [
> (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
> - (match_operand:MVE_2 2 "s_register_operand" "w")]
> - VEORQ))
> + (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
> + (match_operand:MVE_2 2 "s_register_operand" "w")))
> ]
> "TARGET_HAVE_MVE"
> - "veor %q0, %q1, %q2"
> + "veor\t%q0, %q1, %q2"
> [(set_attr "type" "mve_move")
> ])
> +(define_expand "mve_veorq_s<mode>"
> + [
> + (set (match_operand:MVE_2 0 "s_register_operand")
> + (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
> + (match_operand:MVE_2 2 "s_register_operand")))
> + ]
> + "TARGET_HAVE_MVE"
> +)
>
> ;;
> ;; [vhaddq_n_u, vhaddq_n_s])
> @@ -2404,9 +2411,8 @@ (define_insn "mve_vcvttq_f16_f32v8hf"
> (define_insn "mve_veorq_f<mode>"
> [
> (set (match_operand:MVE_0 0 "s_register_operand" "=w")
> - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
> - (match_operand:MVE_0 2 "s_register_operand" "w")]
> - VEORQ_F))
> + (xor:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
> + (match_operand:MVE_0 2 "s_register_operand" "w")))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> "veor %q0, %q1, %q2"
> diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
> index 669c34d..e1263b0 100644
> --- a/gcc/config/arm/neon.md
> +++ b/gcc/config/arm/neon.md
> @@ -747,7 +747,7 @@ (define_insn "bic<mode>3_neon"
> [(set_attr "type" "neon_logic<q>")]
> )
>
> -(define_insn "xor<mode>3"
> +(define_insn "xor<mode>3_neon"
> [(set (match_operand:VDQ 0 "s_register_operand" "=w")
> (xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
> (match_operand:VDQ 2 "s_register_operand" "w")))]
> diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
> index c2076c9..fe240e8 100644
> --- a/gcc/config/arm/unspecs.md
> +++ b/gcc/config/arm/unspecs.md
> @@ -608,7 +608,6 @@ (define_c_enum "unspec" [
> VCMPEQQ_S
> VCMPEQQ_N_S
> VCMPNEQ_N_S
> - VEORQ_S
> VHADDQ_S
> VHADDQ_N_S
> VHSUBQ_S
> @@ -653,7 +652,6 @@ (define_c_enum "unspec" [
> VCMPEQQ_U
> VCMPEQQ_N_U
> VCMPNEQ_N_U
> - VEORQ_U
> VHADDQ_U
> VHADDQ_N_U
> VHSUBQ_U
> @@ -736,7 +734,6 @@ (define_c_enum "unspec" [
> VCMULQ_ROT180_F
> VCMULQ_ROT270_F
> VCMULQ_ROT90_F
> - VEORQ_F
> VMAXNMAQ_F
> VMAXNMAVQ_F
> VMAXNMQ_F
> diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-
> common.md
> index 8d9c89c..030ed82 100644
> --- a/gcc/config/arm/vec-common.md
> +++ b/gcc/config/arm/vec-common.md
> @@ -186,3 +186,10 @@ (define_expand "ior<mode>3"
> (match_operand:VDQ 2 "neon_logic_op2" "")))]
> "ARM_HAVE_<MODE>_ARITH"
> )
> +
> +(define_expand "xor<mode>3"
> + [(set (match_operand:VDQ 0 "s_register_operand" "")
> + (xor:VDQ (match_operand:VDQ 1 "s_register_operand" "")
> + (match_operand:VDQ 2 "s_register_operand" "")))]
> + "ARM_HAVE_<MODE>_ARITH"
> +)
> diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
> b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
> new file mode 100644
> index 0000000..321961f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
> @@ -0,0 +1,61 @@
> +/* { dg-do assemble } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O3" } */
> +
> +#include <stdint.h>
> +
> +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)
> \
> + void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t *
> __restrict__ dest, TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
> + int i; \
> + for (i=0; i<NB; i++) { \
> + dest[i] = a[i] OP b[i];
> \
> + }
> \
> +}
> +
> +#define FUNC_IMM(SIGN, TYPE, BITS, NB, OP, NAME)
> \
> + void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t *
> __restrict__ dest, TYPE##BITS##_t *a) { \
> + int i; \
> + for (i=0; i<NB; i++) { \
> + dest[i] = a[i] OP 1; \
> + }
> \
> +}
> +
> +/* 64-bit vectors. */
> +FUNC(s, int, 32, 2, ^, veor)
> +FUNC(u, uint, 32, 2, ^, veor)
> +FUNC(s, int, 16, 4, ^, veor)
> +FUNC(u, uint, 16, 4, ^, veor)
> +FUNC(s, int, 8, 8, ^, veor)
> +FUNC(u, uint, 8, 8, ^, veor)
> +
> +/* 128-bit vectors. */
> +FUNC(s, int, 32, 4, ^, veor)
> +FUNC(u, uint, 32, 4, ^, veor)
> +FUNC(s, int, 16, 8, ^, veor)
> +FUNC(u, uint, 16, 8, ^, veor)
> +FUNC(s, int, 8, 16, ^, veor)
> +FUNC(u, uint, 8, 16, ^, veor)
> +
> +/* 64-bit vectors. */
> +FUNC_IMM(s, int, 32, 2, ^, veorimm)
> +FUNC_IMM(u, uint, 32, 2, ^, veorimm)
> +FUNC_IMM(s, int, 16, 4, ^, veorimm)
> +FUNC_IMM(u, uint, 16, 4, ^, veorimm)
> +FUNC_IMM(s, int, 8, 8, ^, veorimm)
> +FUNC_IMM(u, uint, 8, 8, ^, veorimm)
> +
> +/* 128-bit vectors. */
> +FUNC_IMM(s, int, 32, 4, ^, veorimm)
> +FUNC_IMM(u, uint, 32, 4, ^, veorimm)
> +FUNC_IMM(s, int, 16, 8, ^, veorimm)
> +FUNC_IMM(u, uint, 16, 8, ^, veorimm)
> +FUNC_IMM(s, int, 8, 16, ^, veorimm)
> +FUNC_IMM(u, uint, 8, 16, ^, veorimm)
> +
> +/* MVE has only 128-bit vectors, so we can vectorize only half of the
> + functions above. */
> +/* Although float16 and float32 types are supported at assembly level,
> + we cannot test them with the '^' operator, so we check only the
> + integer variants. */
> +/* { dg-final { scan-assembler-times {veor\tq[0-9]+, q[0-9]+, q[0-9]+} 12 } }
> */
> --
> 2.7.4
RE: [PATCH v3 1/4] arm: Auto-vectorization for MVE: veor
Kyrylo Tkachov via Gcc-patches Mon, 14 Dec 2020 01:31:54 -0800
- [PATCH v3 1/4] arm: Auto-vectorization for... Christophe Lyon via Gcc-patches
- [PATCH v3 2/4] arm: Auto-vectorizatio... Christophe Lyon via Gcc-patches
- RE: [PATCH v3 2/4] arm: Auto-vect... Kyrylo Tkachov via Gcc-patches
- [PATCH v3 3/4] arm: Auto-vectorizatio... Christophe Lyon via Gcc-patches
- RE: [PATCH v3 3/4] arm: Auto-vect... Kyrylo Tkachov via Gcc-patches
- [PATCH v3 4/4] arm: Auto-vectorizatio... Christophe Lyon via Gcc-patches
- RE: [PATCH v3 4/4] arm: Auto-vect... Kyrylo Tkachov via Gcc-patches
- RE: [PATCH v3 1/4] arm: Auto-vectoriz... Kyrylo Tkachov via Gcc-patches
