> -----Original Message-----
> From: Gcc-patches <gcc-patches-
> bounces+kyrylo.tkachov=arm....@gcc.gnu.org> On Behalf Of Christophe
> Lyon via Gcc-patches
> Sent: Thursday, January 13, 2022 2:56 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH v3 12/15] arm: Convert more load/store MVE builtins to
> predicate qualifiers
>
> This patch covers a few builtins where we do not use the <mode>
> iterator and thus we cannot use <MVE_vpred>.
>
> For v2di instructions, we keep the HI mode for predicates.
Ok.
Thanks,
Kyrill
>
> 2022-01-13 Christophe Lyon <christophe.l...@foss.st.com>
>
> gcc/
> PR target/100757
> PR target/101325
> * config/arm/arm-builtins.c (STRSBS_P_QUALIFIERS): Use predicate
> qualifier.
> (STRSBU_P_QUALIFIERS): Likewise.
> (LDRGBS_Z_QUALIFIERS): Likewise.
> (LDRGBU_Z_QUALIFIERS): Likewise.
> (LDRGBWBXU_Z_QUALIFIERS): Likewise.
> (LDRGBWBS_Z_QUALIFIERS): Likewise.
> (LDRGBWBU_Z_QUALIFIERS): Likewise.
> (STRSBWBS_P_QUALIFIERS): Likewise.
> (STRSBWBU_P_QUALIFIERS): Likewise.
> * config/arm/mve.md: Use VxBI instead of HI.
>
> diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
> index 0b063b5f037..73678a00398 100644
> --- a/gcc/config/arm/arm-builtins.c
> +++ b/gcc/config/arm/arm-builtins.c
> @@ -689,13 +689,13 @@
> arm_strss_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> static enum arm_type_qualifiers
> arm_strsbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_void, qualifier_unsigned, qualifier_immediate,
> - qualifier_none, qualifier_unsigned};
> + qualifier_none, qualifier_predicate};
> #define STRSBS_P_QUALIFIERS (arm_strsbs_p_qualifiers)
>
> static enum arm_type_qualifiers
> arm_strsbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_void, qualifier_unsigned, qualifier_immediate,
> - qualifier_unsigned, qualifier_unsigned};
> + qualifier_unsigned, qualifier_predicate};
> #define STRSBU_P_QUALIFIERS (arm_strsbu_p_qualifiers)
>
> static enum arm_type_qualifiers
> @@ -731,13 +731,13 @@ arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> static enum arm_type_qualifiers
> arm_ldrgbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_none, qualifier_unsigned, qualifier_immediate,
> - qualifier_unsigned};
> + qualifier_predicate};
> #define LDRGBS_Z_QUALIFIERS (arm_ldrgbs_z_qualifiers)
>
> static enum arm_type_qualifiers
> arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate,
> - qualifier_unsigned};
> + qualifier_predicate};
> #define LDRGBU_Z_QUALIFIERS (arm_ldrgbu_z_qualifiers)
>
> static enum arm_type_qualifiers
> @@ -777,7 +777,7 @@
> arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> static enum arm_type_qualifiers
> arm_ldrgbwbxu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate,
> - qualifier_unsigned};
> + qualifier_predicate};
> #define LDRGBWBXU_Z_QUALIFIERS (arm_ldrgbwbxu_z_qualifiers)
>
> static enum arm_type_qualifiers
> @@ -793,13 +793,13 @@
> arm_ldrgbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> static enum arm_type_qualifiers
> arm_ldrgbwbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_none, qualifier_unsigned, qualifier_immediate,
> - qualifier_unsigned};
> + qualifier_predicate};
> #define LDRGBWBS_Z_QUALIFIERS (arm_ldrgbwbs_z_qualifiers)
>
> static enum arm_type_qualifiers
> arm_ldrgbwbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate,
> - qualifier_unsigned};
> + qualifier_predicate};
> #define LDRGBWBU_Z_QUALIFIERS (arm_ldrgbwbu_z_qualifiers)
>
> static enum arm_type_qualifiers
> @@ -815,13 +815,13 @@
> arm_strsbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> static enum arm_type_qualifiers
> arm_strsbwbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_unsigned, qualifier_unsigned, qualifier_const,
> - qualifier_none, qualifier_unsigned};
> + qualifier_none, qualifier_predicate};
> #define STRSBWBS_P_QUALIFIERS (arm_strsbwbs_p_qualifiers)
>
> static enum arm_type_qualifiers
> arm_strsbwbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_unsigned, qualifier_unsigned, qualifier_const,
> - qualifier_unsigned, qualifier_unsigned};
> + qualifier_unsigned, qualifier_predicate};
> #define STRSBWBU_P_QUALIFIERS (arm_strsbwbu_p_qualifiers)
>
> static enum arm_type_qualifiers
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index a8087815c22..9633b7187f6 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -7282,7 +7282,7 @@ (define_insn
> "mve_vstrwq_scatter_base_p_<supf>v4si"
> [(match_operand:V4SI 0 "s_register_operand" "w")
> (match_operand:SI 1 "immediate_operand" "i")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VSTRWSBQ))
> ]
> "TARGET_HAVE_MVE"
> @@ -7371,7 +7371,7 @@ (define_insn
> "mve_vldrwq_gather_base_z_<supf>v4si"
> [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
> (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:SI 2 "immediate_operand" "i")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VLDRWGBQ))
> ]
> "TARGET_HAVE_MVE"
> @@ -7609,7 +7609,7 @@ (define_insn "mve_vldrwq_<supf>v4si"
> (define_insn "mve_vldrwq_z_fv4sf"
> [(set (match_operand:V4SF 0 "s_register_operand" "=w")
> (unspec:V4SF [(match_operand:V4SI 1 "mve_memory_operand"
> "Ux")
> - (match_operand:HI 2 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 2 "vpr_register_operand" "Up")]
> VLDRWQ_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -7629,7 +7629,7 @@ (define_insn "mve_vldrwq_z_fv4sf"
> (define_insn "mve_vldrwq_z_<supf>v4si"
> [(set (match_operand:V4SI 0 "s_register_operand" "=w")
> (unspec:V4SI [(match_operand:V4SI 1 "mve_memory_operand"
> "Ux")
> - (match_operand:HI 2 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 2 "vpr_register_operand" "Up")]
> VLDRWQ))
> ]
> "TARGET_HAVE_MVE"
> @@ -7813,7 +7813,7 @@ (define_insn "mve_vldrhq_gather_offset_z_fv8hf"
> [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
> (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
> (match_operand:V8HI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V8BI 3 "vpr_register_operand" "Up")]
> VLDRHQGO_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -7855,7 +7855,7 @@ (define_insn
> "mve_vldrhq_gather_shifted_offset_z_fv8hf"
> [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
> (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
> (match_operand:V8HI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V8BI 3 "vpr_register_operand" "Up")]
> VLDRHQGSO_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -7897,7 +7897,7 @@ (define_insn "mve_vldrwq_gather_base_z_fv4sf"
> [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
> (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:SI 2 "immediate_operand" "i")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VLDRWQGB_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -7958,7 +7958,7 @@ (define_insn "mve_vldrwq_gather_offset_z_fv4sf"
> [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
> (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VLDRWQGO_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -7980,7 +7980,7 @@ (define_insn
> "mve_vldrwq_gather_offset_z_<supf>v4si"
> [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
> (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VLDRWGOQ))
> ]
> "TARGET_HAVE_MVE"
> @@ -8042,7 +8042,7 @@ (define_insn
> "mve_vldrwq_gather_shifted_offset_z_fv4sf"
> [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
> (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VLDRWQGSO_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -8064,7 +8064,7 @@ (define_insn
> "mve_vldrwq_gather_shifted_offset_z_<supf>v4si"
> [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
> (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VLDRWGSOQ))
> ]
> "TARGET_HAVE_MVE"
> @@ -8104,7 +8104,7 @@ (define_insn "mve_vstrhq_fv8hf"
> (define_insn "mve_vstrhq_p_fv8hf"
> [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
> (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
> - (match_operand:HI 2 "vpr_register_operand" "Up")]
> + (match_operand:V8BI 2 "vpr_register_operand" "Up")]
> VSTRHQ_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -8323,7 +8323,7 @@ (define_insn "mve_vstrwq_p_fv4sf"
> (define_insn "mve_vstrwq_p_<supf>v4si"
> [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
> (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
> - (match_operand:HI 2 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 2 "vpr_register_operand" "Up")]
> VSTRWQ))
> ]
> "TARGET_HAVE_MVE"
> @@ -8576,7 +8576,7 @@ (define_expand
> "mve_vstrhq_scatter_offset_p_fv8hf"
> [(match_operand:V8HI 0 "mve_scatter_memory")
> (match_operand:V8HI 1 "s_register_operand")
> (match_operand:V8HF 2 "s_register_operand")
> - (match_operand:HI 3 "vpr_register_operand")
> + (match_operand:V8BI 3 "vpr_register_operand")
> (unspec:V4SI [(const_int 0)] VSTRHQSO_F)]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> {
> @@ -8594,7 +8594,7 @@ (define_insn
> "mve_vstrhq_scatter_offset_p_fv8hf_insn"
> [(match_operand:SI 0 "register_operand" "r")
> (match_operand:V8HI 1 "s_register_operand" "w")
> (match_operand:V8HF 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V8BI 3 "vpr_register_operand" "Up")]
> VSTRHQSO_F))]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> "vpst\;vstrht.16\t%q2, [%0, %q1]"
> @@ -8635,7 +8635,7 @@ (define_expand
> "mve_vstrhq_scatter_shifted_offset_p_fv8hf"
> [(match_operand:V8HI 0 "memory_operand" "=Us")
> (match_operand:V8HI 1 "s_register_operand" "w")
> (match_operand:V8HF 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")
> + (match_operand:V8BI 3 "vpr_register_operand" "Up")
> (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> {
> @@ -8654,7 +8654,7 @@ (define_insn
> "mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn"
> [(match_operand:SI 0 "register_operand" "r")
> (match_operand:V8HI 1 "s_register_operand" "w")
> (match_operand:V8HF 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V8BI 3 "vpr_register_operand" "Up")]
> VSTRHQSSO_F))]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> "vpst\;vstrht.16\t%q2, [%0, %q1, uxtw #1]"
> @@ -8691,7 +8691,7 @@ (define_insn "mve_vstrwq_scatter_base_p_fv4sf"
> [(match_operand:V4SI 0 "s_register_operand" "w")
> (match_operand:SI 1 "immediate_operand" "i")
> (match_operand:V4SF 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VSTRWQSB_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -8740,7 +8740,7 @@ (define_expand
> "mve_vstrwq_scatter_offset_p_fv4sf"
> [(match_operand:V4SI 0 "mve_scatter_memory")
> (match_operand:V4SI 1 "s_register_operand")
> (match_operand:V4SF 2 "s_register_operand")
> - (match_operand:HI 3 "vpr_register_operand")
> + (match_operand:V4BI 3 "vpr_register_operand")
> (unspec:V4SI [(const_int 0)] VSTRWQSO_F)]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> {
> @@ -8758,7 +8758,7 @@ (define_insn
> "mve_vstrwq_scatter_offset_p_fv4sf_insn"
> [(match_operand:SI 0 "register_operand" "r")
> (match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:V4SF 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VSTRWQSO_F))]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> "vpst\;vstrwt.32\t%q2, [%0, %q1]"
> @@ -8771,7 +8771,7 @@ (define_expand
> "mve_vstrwq_scatter_offset_p_<supf>v4si"
> [(match_operand:V4SI 0 "mve_scatter_memory")
> (match_operand:V4SI 1 "s_register_operand")
> (match_operand:V4SI 2 "s_register_operand")
> - (match_operand:HI 3 "vpr_register_operand")
> + (match_operand:V4BI 3 "vpr_register_operand")
> (unspec:V4SI [(const_int 0)] VSTRWSOQ)]
> "TARGET_HAVE_MVE"
> {
> @@ -8789,7 +8789,7 @@ (define_insn
> "mve_vstrwq_scatter_offset_p_<supf>v4si_insn"
> [(match_operand:SI 0 "register_operand" "r")
> (match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VSTRWSOQ))]
> "TARGET_HAVE_MVE"
> "vpst\;vstrwt.32\t%q2, [%0, %q1]"
> @@ -8858,7 +8858,7 @@ (define_expand
> "mve_vstrwq_scatter_shifted_offset_p_fv4sf"
> [(match_operand:V4SI 0 "mve_scatter_memory")
> (match_operand:V4SI 1 "s_register_operand")
> (match_operand:V4SF 2 "s_register_operand")
> - (match_operand:HI 3 "vpr_register_operand")
> + (match_operand:V4BI 3 "vpr_register_operand")
> (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> {
> @@ -8877,7 +8877,7 @@ (define_insn
> "mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn"
> [(match_operand:SI 0 "register_operand" "r")
> (match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:V4SF 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VSTRWQSSO_F))]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]"
> @@ -8890,7 +8890,7 @@ (define_expand
> "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si"
> [(match_operand:V4SI 0 "mve_scatter_memory")
> (match_operand:V4SI 1 "s_register_operand")
> (match_operand:V4SI 2 "s_register_operand")
> - (match_operand:HI 3 "vpr_register_operand")
> + (match_operand:V4BI 3 "vpr_register_operand")
> (unspec:V4SI [(const_int 0)] VSTRWSSOQ)]
> "TARGET_HAVE_MVE"
> {
> @@ -8909,7 +8909,7 @@ (define_insn
> "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn"
> [(match_operand:SI 0 "register_operand" "r")
> (match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VSTRWSSOQ))]
> "TARGET_HAVE_MVE"
> "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]"
> @@ -9376,7 +9376,7 @@ (define_insn
> "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
> [(match_operand:V4SI 1 "s_register_operand" "0")
> (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:HI 4 "vpr_register_operand")]
> + (match_operand:V4BI 4 "vpr_register_operand")]
> VSTRWSBWBQ))
> (set (match_operand:V4SI 0 "s_register_operand" "=w")
> (unspec:V4SI [(match_dup 1) (match_dup 2)]
> @@ -9427,7 +9427,7 @@ (define_insn
> "mve_vstrwq_scatter_base_wb_p_fv4sf"
> [(match_operand:V4SI 1 "s_register_operand" "0")
> (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
> (match_operand:V4SF 3 "s_register_operand" "w")
> - (match_operand:HI 4 "vpr_register_operand")]
> + (match_operand:V4BI 4 "vpr_register_operand")]
> VSTRWQSBWB_F))
> (set (match_operand:V4SI 0 "s_register_operand" "=w")
> (unspec:V4SI [(match_dup 1) (match_dup 2)]
> @@ -9551,7 +9551,7 @@ (define_expand
> "mve_vldrwq_gather_base_wb_z_<supf>v4si"
> [(match_operand:V4SI 0 "s_register_operand")
> (match_operand:V4SI 1 "s_register_operand")
> (match_operand:SI 2 "mve_vldrd_immediate")
> - (match_operand:HI 3 "vpr_register_operand")
> + (match_operand:V4BI 3 "vpr_register_operand")
> (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
> "TARGET_HAVE_MVE"
> {
> @@ -9566,7 +9566,7 @@ (define_expand
> "mve_vldrwq_gather_base_nowb_z_<supf>v4si"
> [(match_operand:V4SI 0 "s_register_operand")
> (match_operand:V4SI 1 "s_register_operand")
> (match_operand:SI 2 "mve_vldrd_immediate")
> - (match_operand:HI 3 "vpr_register_operand")
> + (match_operand:V4BI 3 "vpr_register_operand")
> (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
> "TARGET_HAVE_MVE"
> {
> @@ -9585,7 +9585,7 @@ (define_insn
> "mve_vldrwq_gather_base_wb_z_<supf>v4si_insn"
> [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
> (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1")
> (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
> - (match_operand:HI 4 "vpr_register_operand" "Up")
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")
> (mem:BLK (scratch))]
> VLDRWGBWBQ))
> (set (match_operand:V4SI 1 "s_register_operand" "=&w")
> @@ -9659,7 +9659,7 @@ (define_expand
> "mve_vldrwq_gather_base_wb_z_fv4sf"
> [(match_operand:V4SI 0 "s_register_operand")
> (match_operand:V4SI 1 "s_register_operand")
> (match_operand:SI 2 "mve_vldrd_immediate")
> - (match_operand:HI 3 "vpr_register_operand")
> + (match_operand:V4BI 3 "vpr_register_operand")
> (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> {
> @@ -9675,7 +9675,7 @@ (define_expand
> "mve_vldrwq_gather_base_nowb_z_fv4sf"
> [(match_operand:V4SF 0 "s_register_operand")
> (match_operand:V4SI 1 "s_register_operand")
> (match_operand:SI 2 "mve_vldrd_immediate")
> - (match_operand:HI 3 "vpr_register_operand")
> + (match_operand:V4BI 3 "vpr_register_operand")
> (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> {
> @@ -9694,7 +9694,7 @@ (define_insn
> "mve_vldrwq_gather_base_wb_z_fv4sf_insn"
> [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
> (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1")
> (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
> - (match_operand:HI 4 "vpr_register_operand" "Up")
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")
> (mem:BLK (scratch))]
> VLDRWQGBWB_F))
> (set (match_operand:V4SI 1 "s_register_operand" "=&w")
> --
> 2.25.1
RE: [PATCH v3 12/15] arm: Convert more load/store MVE builtins to predicate qualifiers
Kyrylo Tkachov via Gcc-patches Thu, 27 Jan 2022 08:56:54 -0800
- Re: [PATCH v3 0... Richard Sandiford via Gcc-patches
- Re: [PATCH ... Richard Sandiford via Gcc-patches
- Re: [PATCH ... Christophe Lyon via Gcc-patches
- Re: [PATCH ... Richard Sandiford via Gcc-patches
- [PATCH v3 08/15] arm: Implement auto-... Christophe Lyon via Gcc-patches
- RE: [PATCH v3 08/15] arm: Implem... Kyrylo Tkachov via Gcc-patches
- [PATCH v3 09/15] arm: Fix vcond_mask ... Christophe Lyon via Gcc-patches
- RE: [PATCH v3 09/15] arm: Fix vc... Kyrylo Tkachov via Gcc-patches
- [PATCH v3 10/15] arm: Convert remaini... Christophe Lyon via Gcc-patches
- [PATCH v3 12/15] arm: Convert more lo... Christophe Lyon via Gcc-patches
- RE: [PATCH v3 12/15] arm: Conver... Kyrylo Tkachov via Gcc-patches
- [PATCH v3 13/15] arm: Convert more MV... Christophe Lyon via Gcc-patches
- RE: [PATCH v3 13/15] arm: Conver... Kyrylo Tkachov via Gcc-patches
- [PATCH v3 14/15] arm: Add VPR_REG to ... Christophe Lyon via Gcc-patches
- [PATCH v3 15/15] arm: Fix constraint ... Christophe Lyon via Gcc-patches
- [arm] MVE: Relax addressing mode... Andre Vieira (lists) via Gcc-patches
- Re: [arm] MVE: Relax address... Christophe Lyon via Gcc-patches
- Re: [arm] MVE: Relax add... Andre Vieira (lists) via Gcc-patches
- RE: [arm] MVE: Relax... Kyrylo Tkachov via Gcc-patches
- Re: [PATCH v3 00/15] ARM/MVE use vect... Christophe Lyon via Gcc-patches
- Re: [PATCH v3 00/15] ARM/MVE use... Richard Biener via Gcc-patches
