, Yanzhang
Subject: RE: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
Thanks Juzhe for reviewing. I see, this way may have even smaller code change
which treats the zvfhmin as minimal base sub extension.
I will have a try for PATCH V6.
Pan
From: juzhe.zh...@rivai.ai
; Li,
Pan2 ; Wang, Yanzhang
Subject: Re: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
In this patch, you add TARGET_ZVFH into VF iterator which is not correct.
When TARGET_ZVFH is true, TARGET_ZVFHMIN is always true.
For vfadd, it is true we should enable "vfadd" for T
In this patch, you add TARGET_ZVFH into VF iterator which is not correct.
When TARGET_ZVFH is true, TARGET_ZVFHMIN is always true.
For vfadd, it is true we should enable "vfadd" for TARGET_ZVFH
For vle16, we should enable for TARGET_ZVFHMIN.
This patch will disable both "vle16" and "vfadd" for F
I am not sure for load/stores of FP16 vector should be gated by ZVFHMIN or ZVFH?
Since IMHO, load/stores of FP16 is no different from load/stores of INT16?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-07 16:06
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang
