; jeffreyalaw
; Robin Dapp
Subject: Re: Re: [PATCH] RISC-V: Add RVV narrow shift right lowering
auto-vectorization
Yes, change all define_insn_and_split to that style, "TARGET_VECTOR &&
can_create_pseudo_p ()"/ "&& 1", my understanding is all those patterns
Yes, change all define_insn_and_split to that style, "TARGET_VECTOR &&
can_create_pseudo_p ()"/ "&& 1", my understanding is all those
patterns should only work before RA, so all using "TARGET_VECTOR &&
can_create_pseudo_p ()" is more reasonable.
On Mon, Jun 12, 2023 at 8:41 PM
You mean change all split pattern like this ?
;; This helps to match zero_extend + sign_extend + fma.
(define_insn_and_split "*zero_sign_extend_fma"
[(set (match_operand:VWEXTI 0 "register_operand")
(plus:VWEXTI
(mult:VWEXTI
(zero_extend:VWEXTI
(match_operand: 2
