y (1,1) size.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-02 17:39
To: juzhe.zhong\@rivai.ai
CC: rguenther; pan2.li; gcc-patches; incarnation.p.lee; Kito.cheng
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Thanks for the explanation about the sizes.
types but isn't
sizeof (vbool8_t) part of the ABI and thus its TYPE_SIZE / GET_MODE_SIZE
are relevant there? It might of course be that you can never have
these types as part of aggregates, arrays or objects of them address-taken
in which case the issue is moot?
Richard.
>
> juzhe.
(vbool8_t) part of the ABI and thus its TYPE_SIZE / GET_MODE_SIZE
are relevant there? It might of course be that you can never have
these types as part of aggregates, arrays or objects of them address-taken
in which case the issue is moot?
Richard.
>
> juzhe.zh...@rivai.ai
>
> From: Rich
@rivai.ai<mailto:juzhe.zh...@rivai.ai>
> mailto:juzhe.zh...@rivai.ai>>
> Sent: Wednesday, March 1, 2023 10:19 PM
> To: rguenther mailto:rguent...@suse.de>>
> Cc: richard.sandiford
> mailto:richard.sandif...@arm.com>>; gcc-patches
> mailto:gcc-patches@gcc.
isor (like
> 1/8 or 2/8) cases.
>
> Could you please share your professional suggestions about this? Thank you
> all again and have a nice day!
>
> Pan
>
> From: juzhe.zh...@rivai.ai
> Sent: Wednesday, March 1, 2023 10:19 PM
> To: rguenther
> Cc: richard.sandiford ; gc
generate"
Pan
From: Li, Pan2
Sent: Wednesday, March 1, 2023 23:42
To: juzhe.zh...@rivai.ai ; rguenther
Cc: richard.sandiford ; gcc-patches
; Pan Li ; kito.cheng
Subject: RE: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Thanks all for so much valuable a
an2
; kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
>> So given the above I think that modeling the size as being the same
>> but with accurate precision would work. It's then only the size of the
>> padding in bytes we cannot represent with
cision even though
they have same bytesize.
First we emit vsetvl e8mf8 +vsm for VNx1BI
Then we emit vsetvl e8mf8 + vlm for VNx2BI
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-03-01 22:03
To: juzhe.zhong
CC: richard.sandiford; gcc-patches; Pan Li; pan2.li; kito.cheng
Subject: Re: Re
On Wed, 1 Mar 2023, Richard Biener wrote:
> On Wed, 1 Mar 2023, juzhe.zh...@rivai.ai wrote:
>
> > Let's me first introduce RVV load/store basics and stack allocation.
> > For scalable vector memory allocation, we allocate memory according to
> > machine vector-length.
> > To get this CPU
ata memory access load store behavior.
So given the above I think that modeling the size as being the same
but with accurate precision would work. It's then only the size of the
padding in bytes we cannot represent with poly-int which should be fine.
Correct?
Richard.
> Thanks.
>
>
>
e aware of this . Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-03-01 21:50
To: richard.sandiford; gcc-patches
CC: rguenther; Pan Li; pan2.li; kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Let's me first introduce RVV load/store basi
-01 21:19
To: Pan Li via Gcc-patches
CC: Richard Biener; Pan Li; juzhe.zhong\@rivai.ai; pan2.li; Kito.cheng
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Pan Li via Gcc-patches writes:
> I am not very familiar with the memory pattern, maybe juzhe can provid
tches
Cc: incarnation.p.lee ; pan2.li
; Kito.cheng ; rguenther
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Actually, we just want to differentiate VNx1BI VNx2BI VNx4BI VNx8BI, and they
are considered the same in GCC which produce BUG in RVV currently.
This patch is j
?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-01 20:03
To: 盼 李 via Gcc-patches
CC: 盼 李; juzhe.zhong\@rivai.ai; pan2.li; Kito.cheng; rguenther
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
盼 李 via Gcc-patches writes:
> Just have a t
; pan2.li
Cc: incarnation.p.lee ; gcc-patches
; Kito.cheng ; rguenther
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
>> Is it right that, for RVV, a load or store of [4,4] will access [8,8]
>>bits, even when that means accessing fully-unused bytes? E.g.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-01 18:11
To: Li\, Pan2
CC: 盼 李; incarnation.p.lee--- via Gcc-patches; juzhe.zhong\@rivai.ai;
kito.cheng\@sifive.com; rguenther\@suse.de
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
"Li, Pan2"
; jeffreyalaw
Subject: RE: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Hi Richard Sandiford,
Looks like you are busy and stuck in some important work right now, could you
please help to share something like ETA if possible? Then we may have a better
plan for the RVV intrinsic support
.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, February 24, 2023 1:08 PM
To: kito.cheng ; Li, Pan2
Cc: richard.sandiford ; incarnation.p.lee
; gcc-patches ;
Kito.cheng ; rguenther ; jeffreyalaw
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Hi,
It's been
...@rivai.ai
From: Kito Cheng
Date: 2023-02-21 16:28
To: Li, Pan2
CC: richard.sandif...@arm.com; juzhe.zhong; incarnation.p@outlook.com;
gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; Richard Biener
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Hi Richard Sandiford
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