Committed, thanks Kito and Juzhe, will fix the issue we discussed soon.
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, June 6, 2023 9:48 AM
To: juzhe.zh...@rivai.ai
Cc: kito.cheng ; Li, Pan2 ;
gcc-patches ; Wang, Yanzhang
Subject: Re: Re: [PATCH v1] RISC-V: Support RVV FP16
OK for landing this patch first, and fix by follow up patches.
On Tue, Jun 6, 2023 at 9:41 AM juzhe.zh...@rivai.ai
wrote:
>
> I think we should split instructions pattern which belongs to ZVFHMIN.
> And add ZVFH gating into all original iterator for example: VF VWFetc.
>
> ___
I think we should split instructions pattern which belongs to ZVFHMIN.
And add ZVFH gating into all original iterator for example: VF VWFetc.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-06 09:32
To: juzhe.zh...@rivai.ai
CC: pan2.li; gcc-patches; Kito.cheng; yanzhang.wang
Subject: R
previous one?
Both works for me.
Pan
From: juzhe.zh...@rivai.ai
Sent: Tuesday, June 6, 2023 9:39 AM
To: kito.cheng
Cc: Li, Pan2 ; gcc-patches ;
Kito.cheng ; Wang, Yanzhang
Subject: Re: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction
floating-point intrinsic API
Oh. YES. Thanks
Oh. YES. Thanks for catching this.
VF will be used in autovec for example: vfadd.
When specify zfhmin, the vfadd autovec will be enabled unexpectedly.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-06 09:32
To: juzhe.zh...@rivai.ai
CC: pan2.li; gcc-patches; Kito.cheng; yanzhang.wang
Subje
