Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-18 Thread Vladimir Makarov
On 12-10-15 8:06 AM, Richard Sandiford wrote: Vladimir Makarov writes: if that's accurate. I dropped the term "reload pseudo" because of the general comment in my earlier reply about the use of "reload pseudo" when the code seems to include inheritance and split pseudos too. There is no inher

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-18 Thread Vladimir Makarov
On 12-10-17 7:24 AM, Richard Sandiford wrote: Thanks for all the updates. Vladimir Makarov writes: + /* index * scale + disp => new base + index * scale */ + enum reg_class cl = base_reg_class (mode, as, SCRATCH, SCRATCH); + + lra_assert (INDEX_REG_CLASS != NO_REGS); +

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-17 Thread Steven Bosscher
On Wed, Oct 17, 2012 at 9:53 PM, Vladimir Makarov wrote: > On 12-10-15 12:49 PM, Richard Sandiford wrote: >> Getting rid of reload always seemed like a pipe dream, and if the only >> known drawback of this replacement is that it takes a while on extreme >> testcases, that's an amazing achievement.

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-17 Thread Vladimir Makarov
On 12-10-15 12:49 PM, Richard Sandiford wrote: Hi Vlad, Some comments about the rest of LRA. Nothing major here... Vladimir Makarov writes: +/* Info about register in an insn. */ +struct lra_insn_reg +{ + /* The biggest mode through which the insn refers to the register + (remember the

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-17 Thread Richard Sandiford
Thanks for all the updates. Vladimir Makarov writes: >>> + /* index * scale + disp => new base + index * scale */ >>> + enum reg_class cl = base_reg_class (mode, as, SCRATCH, SCRATCH); >>> + >>> + lra_assert (INDEX_REG_CLASS != NO_REGS); >>> + new_reg = lra_create_new_reg (Pmode,

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-16 Thread Vladimir Makarov
On 12-10-12 10:29 AM, Richard Sandiford wrote: Hi Vlad, Comments for the rest of ira-constraints.c. Vladimir Makarov writes: + saved_base_reg = saved_base_reg2 = saved_index_reg = NULL_RTX; + change_p = equiv_address_substitution (&ad, addr_loc, mode, as, code); + if (ad.base_reg_loc != NU

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-15 Thread Richard Sandiford
Hi Vlad, Some comments about the rest of LRA. Nothing major here... Vladimir Makarov writes: > +/* Info about register in an insn. */ > +struct lra_insn_reg > +{ > + /* The biggest mode through which the insn refers to the register > + (remember the register can be accessed through a subr

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-15 Thread Richard Sandiford
Vladimir Makarov writes: >> if that's accurate. I dropped the term "reload pseudo" because of >> the general comment in my earlier reply about the use of "reload pseudo" >> when the code seems to include inheritance and split pseudos too. > There is no inheritance and splitting yet. It is done a

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-13 Thread Richard Sandiford
I'm having to correct my own comments again, sorry. Richard Sandiford writes: >> + /* If this is post-increment, first copy the location to the reload reg. >> */ >> + if (post && real_in != result) >> +emit_insn (gen_move_insn (result, real_in)); > > Nit, but real_in != result can never b

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-12 Thread Richard Sandiford
Vladimir Makarov writes: >>> +/* Info about pseudo used during the assignment pass. Thread is a set >>> + of connected reload and inheritance pseudos with the same set of >>> + available hard reg set. Thread is a pseudo itself for other >>> + cases. */ >>> +struct regno_assign_info >> May

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-12 Thread Richard Sandiford
Hi Vlad, Comments for the rest of ira-constraints.c. Vladimir Makarov writes: > + saved_base_reg = saved_base_reg2 = saved_index_reg = NULL_RTX; > + change_p = equiv_address_substitution (&ad, addr_loc, mode, as, code); > + if (ad.base_reg_loc != NULL) > +{ > + if (process_addr_reg >

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-11 Thread Vladimir Makarov
On 10/04/2012 11:50 AM, Richard Sandiford wrote: Hi Vlad, This message is for lra-assigns.c. Sorry for the piecemeal reviews, never sure when I'll get time... +/* This file contains a pass mostly assigning hard registers to reload + pseudos. There is no any RTL code transformation on this

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-10 Thread Vladimir Makarov
On 12-10-03 7:11 AM, Richard Sandiford wrote: Hi Vlad, Some comments on lra-spills.c and lra-coalesce.c. + The pass creates necessary stack slots and assign spilled pseudos + to the stack slots in following way: s/assign/assigns/ Fixed. + (or insn memory constraints) might be not sati

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-10 Thread Richard Sandiford
Sorry, reading back in different surroundings made me notice a couple of silly errors: Richard Sandiford writes: > E.g.: > > if ((*loc = get_equiv_substitution (reg)) != reg) > ...as above... > if (*loc != reg || !in_class_p (reg, cl, &new_class)) > ...as above... > else if (new_cla

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-04 Thread Richard Sandiford
Hi Vlad, This message is for lra-assigns.c. Sorry for the piecemeal reviews, never sure when I'll get time... > +/* This file contains a pass mostly assigning hard registers to reload > + pseudos. There is no any RTL code transformation on this pass. Maybe: /* This file's main objective is

Re: RFC: LRA for x86/x86-64 [7/9] -- continuation

2012-10-03 Thread Richard Sandiford
Hi Vlad, Some comments on lra-spills.c and lra-coalesce.c. > + The pass creates necessary stack slots and assign spilled pseudos > + to the stack slots in following way: s/assign/assigns/ > + (or insn memory constraints) might be not satisfied any more. s/might be not/might not be/ > +