> vadd tama
> vse.v
> VSETVL PASS will choose to set tama for vse.v
>
> vadd tumu
> vse.v
> VSETVL PASS will choose to set tumu for vse.v
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Jeff Law
> Date: 2022-12-17 04:01
> To: juzhe.zhong; gcc-patches
> CC: kito.cheng;
will choose to set tumu for vse.v
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2022-12-17 04:01
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Remove unit-stride store from ta attribute
On 12/14/22 04:36, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
&g
On Fri, Dec 16, 2022 at 1:59 PM Palmer Dabbelt wrote:
>
> On Fri, 16 Dec 2022 12:01:04 PST (-0800), jeffreya...@gmail.com wrote:
> >
> >
> > On 12/14/22 04:36, juzhe.zh...@rivai.ai wrote:
> >> From: Ju-Zhe Zhong
> >>
> >> Since store instructions doesn't care about tail policy, we remove
> >> vst
On Fri, 16 Dec 2022 12:01:04 PST (-0800), jeffreya...@gmail.com wrote:
On 12/14/22 04:36, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
Since store instructions doesn't care about tail policy, we remove
vste from "ta" attribute. Hence, we could have more fusion chances
and better optimizati
On 12/14/22 04:36, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
Since store instructions doesn't care about tail policy, we remove
vste from "ta" attribute. Hence, we could have more fusion chances
and better optimization.
gcc/ChangeLog:
* config/riscv/vector.md: Remove vste.
Ju
