On 2020-02-24 4:54 a.m., Christophe Lyon wrote:
Hi,
On Sun, 23 Feb 2020 at 22:26, Vladimir Makarov wrote:
The following patch is for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93564
The patch was successfully bootstrapped on x86-64 and benchmarked on
SPEC2000.
It seems this patch
On 2020-02-27 7:33 a.m., Andrew Stubbs wrote:
On 26/02/2020 15:16, Andrew Stubbs wrote:
The problem appears to be that the high-part of a register pair is
not marked as "ever live". I'm trying to figure out whether this is
some kind of target-specific issue that has merely been exposed, but
On 26/02/2020 15:16, Andrew Stubbs wrote:
The problem appears to be that the high-part of a register pair is not
marked as "ever live". I'm trying to figure out whether this is some
kind of target-specific issue that has merely been exposed, but it's
difficult to see what's going on. I'm
On 23/02/2020 21:25, Vladimir Makarov wrote:
The following patch is for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93564
The patch was successfully bootstrapped on x86-64 and benchmarked on
SPEC2000.
Since this patch I get an ICE with checking enabled, for amdgcn-amdhsa:
during RTL
Hi,
On Sun, 23 Feb 2020 at 22:26, Vladimir Makarov wrote:
>
> The following patch is for
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93564
>
> The patch was successfully bootstrapped on x86-64 and benchmarked on
> SPEC2000.
>
It seems this patch causes regression on some arm cores (seen
The following patch is for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93564
The patch was successfully bootstrapped on x86-64 and benchmarked on
SPEC2000.
commit 3133bed5d0327e8a9cd0a601b7ecdb9de4fc825d
Author: Vladimir N. Makarov
Date: Sun Feb 23 16:20:05 2020 -0500
Changing cost
