[snip]
> Also, the gEDA/SPICE tutorial mentions 'model' and 'type' attributes
> which are not available on the standard attribute list (like value,
> netname etc). Do I have to include them manually?
>
I would be happy to added them to the standard list, but what
are the ones that are m
[snip]
>> Now suppose I want to label my buses for the same purpose: as a
>> documentation aid for others looking at my schematics. Of course I can
>> just stick a text object next to it that isn't of name=value form, but
>> it seems to me that an attribute would be more appropriate, even if no
>>
Matthias Wenzel wrote:
Matthias Wenzel wrote:
Thanks for the effort, but the pads overlap:
http://mazzoo.de/d/QFN16_3_EP_b0rken.png
:(
geometries (metak & silk) are in the datasheet.
OK, I fixed it myself.
http://mazzoo.de/d/QFN16_3_EP.png
now it _looks_ good. Please verify before using it!
On Tuesday 17 October 2006 15:59, John Coppens wrote:
> I was (trying to) simulate a switching power supply,
A warning ... ngspice has some problems with its step size
control that sometimes gives wrong results, particularly on
circuits like switch mode power supplies. The problem is shows
wi
On Tuesday 17 October 2006 11:51, John Coppens wrote:
> 2) Another version of the circuit causes:
>
> Found unknown component. Refdes = L1
>
> L1 is an inductor, shown correctly on the schematic, and
> included in the generated netlist as:
>
> L1 vlin vlout 180u
>
> which I suppose is corr
> OK, let's review: buses on schematics are a documentation feature, i.e.,
> intended not for tools but for other engineers looking at the drawing,
> right?
Yes.
> Now suppose I want to label my buses for the same purpose: as a
> documentation aid for others looking at my schematics. Of course
DJ Delorie <[EMAIL PROTECTED]> wrote:
> A "bus" is purely decoration. Everything ignores it. All that
> matters is the nets that connect to it and THEY must have net names,
> as usual. Yes, each little connecting net has to be named. That's
> what does the actual work.
OK, thanks for the clar
Em Seg, 2006-10-16 às 17:40 +0200, Carlos Nieves Ónega escreveu:
Just curious, do you have any suggestion to improve this feature? why
don't you like it?
Regards,
Carlos
Tanks Carlos,
Well, I just don´t like because we work with some norms about design.
I.E.
> 1. There doesn't seem to be any way to indicate how wide a bus is in
>bits, i.e., how many nets should it turn into. Does gEDA not care?
>How can it not care? How many nets is the netlister going to
>generate for a bus?
A "bus" is purely decoration. Everything ignores it. All th
Hello again fellow gEDA users,
As my OSDCU design is a microprocessor system of moderate complexity, I
need to use buses on my schematics -- for my microprocessor's address
and data buses and everything connected to them. I haven't been able to
find any real documentation on buses in gEDA/gaf (al
Matthias Wenzel wrote:
> Thanks for the effort, but the pads overlap:
> http://mazzoo.de/d/QFN16_3_EP_b0rken.png
>
> :(
>
> geometries (metak & silk) are in the datasheet.
OK, I fixed it myself.
http://mazzoo.de/d/QFN16_3_EP.png
now it _looks_ good. Please verify before using it!
I did it thro
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