Hi Kiu,
I think it's best to only alter the silkscreen diameter to 197 mil (or 5 mm)
The pin distance should be 100 mil (is 2.54 mm).
Kind regards,
Bert Timmerman.
-Oorspronkelijk bericht-
Van: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] Namens kiu
Verzonden: zondag 11 februari 2007
I'm new to gaf/pcb. My first layout caused an infinite loop in gsch2pcb.
This seems to be due to an infinite loop in the SIL m4 macro, which is
due to two things:
1) The macro has what I'm guessing is cut'n'paste code left from DIL
to draw dividers on the silkscreen pins/2-1 times instead of
On Sun, 2007-02-11 at 08:25 +0100, Bert Timmerman wrote:
The directories have not been merged, that is, m4 derived footprints in the
newlib format live in lib/pcblib-newlib and the newlib contains the
footprints according to the newlib format.
Confused, you won't be after the next episode
Hi guys --
We had a very successful code sprint yesterday! At one time we had
about 14 people active on IRC, and 4 people hacking in the room at
MIT! A very nice turn-out!
Better yet, a lot of bugs were squished, and a lot of new stuff made
it into CVS! I personally was able to get some nice
Hi Bert,
El dom, 11-02-2007 a las 12:29 +0100, Bert Timmerman escribió:
I tried to contact Intermedius Design Integration two years ago in december
2004, and they never replied.
From what I recall from looking up their website is that Intermedius Design
Integration was a one-man company.
On Sat, 10 Feb 2007 17:00:18 -0500
DJ Delorie [EMAIL PROTECTED] wrote:
The lesstif HID now has printer calibration. It prints a test page,
you measure it, tell it the numbers, and it adjusts future printouts
to compensate.
Wery good i have asked for that before
And now it fixt.
Thanks
Hi,
I am new to gEDA and beginning my first non-trivial project. I have
experimented with different layouts trying to get a feel for the pcb
program and cannot seem to get the polygon/rectangle fill to work
properly. It seems other layout programs (eagle,protel) allow you to
perform the
Hello thre,
I'm trying to make a VHDL file from a mere simple half adder schematic:
http://tux.u-strasbg.fr/~chit/half_adder/adder.sch
with:
gnetlist -g vhdl adder.sch -o output.vhdl
http://tux.u-strasbg.fr/~chit/half_adder/output.vhdl
However, I don't know how to create an entity with gschem.
DJ Delorie wrote:
The lesstif HID now has printer calibration. It prints a test page,
you measure it, tell it the numbers, and it adjusts future printouts
to compensate.
Way to go, DJ!
JG
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geda-user@moria.seul.org
Menu- settings - New lines, arcs, clear polygons is probably unset, so when
you make a line it connects to the polygon, which is your ground plane.
to fix:
delete your polygons.
type :select(all)
:changeclearsize(selected, 1000)
then redraw your polygon. that _should_ work
-Lares
On
El dom, 11-02-2007 a las 20:03 +0100, Chitlesh GOORAH escribió:
[snip]
I'm trying to make a VHDL file from a mere simple half adder schematic:
http://tux.u-strasbg.fr/~chit/half_adder/adder.sch
with:
gnetlist -g vhdl adder.sch -o output.vhdl
From: Chitlesh GOORAH [EMAIL PROTECTED]
Subject: gEDA-user: vhdl and gschem
Date: Sun, 11 Feb 2007 20:03:47 +0100
Message-ID: [EMAIL PROTECTED]
Hi!
Hello thre,
I'm trying to make a VHDL file from a mere simple half adder schematic:
http://tux.u-strasbg.fr/~chit/half_adder/adder.sch
with:
On Sun, 11 Feb 2007 14:45:40 -0400, Ryan Seal wrote:
It seems other layout programs (eagle,protel) allow you to
perform the routes, get everything the way you want it, and then apply a
fill over the existing board. Normally, this will provide proper
clearance around parts, traces, vias,
On 2/11/07, Magnus Danielson wrote:
However, in general what you do want to do is to design in input and output
You want to go into the VHDL symbol table and use ipad-1, opad-1 and iopad-1
which will map over to VHDL in, out and inout declarations of Std_Logic type.
Assign the value of these to
Something like this. (Still preliminary)
typedef struct /* vector for objects and such */
{
PointType X;
PointType Y;
PointType x0;
PointType y0;
float angle; /* Radians NOT degrees (math.h reasons)*/
double lenght;
} vector_t,
Peter Clifton wrote:
On Sun, 2007-02-11 at 08:25 +0100, Bert Timmerman wrote:
The directories have not been merged, that is, m4 derived footprints in the
newlib format live in lib/pcblib-newlib and the newlib contains the
footprints according to the newlib format.
Confused, you won't be
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