On 30 Apr 2007, at 10:20:13 PM, Stephen Williams wrote:
I've looked at the thread in comp.lang.verilog. The parameter
definition circularity problem is nasty, but a carefully contained
extension (a la the way Modelsim handles it) seems plausible.
This is a good candidate for the Feature Request
Stephen Williams wrote:
[EMAIL PROTECTED] wrote:
Basically, I'm whining for a feature.
I've looked at the thread in comp.lang.verilog. The parameter
definition circularity problem is nasty, but a carefully contained
extension (a la the way Modelsim handles it) seems plausible.
This is a good
On 1 May 2007, at 4:02:28 AM, Evan Lavelle wrote:
Stephen Williams wrote:
[EMAIL PROTECTED] wrote:
Basically, I'm whining for a feature.
I've looked at the thread in comp.lang.verilog. The parameter
definition circularity problem is nasty, but a carefully contained
extension (a la the way
[EMAIL PROTECTED] wrote:
However, the lack of such a feature shows
the poor thought of Verilog's designers.
Sssh they're out there somewhere, and they may be listening.
The burden is on the programmer, not
the tools.
The main problem with both Verilog and VHDL is that they're both
On Tue, May 01, 2007 at 08:01:48PM -0700, Matt Ettus wrote:
I get the following errors when trying to compile a dual-ported ram in
icarus. I'm sure my syntax must be bad somewhere, but I can't see
where.
I get different errors, which go away if I replace 2**ADDR_WIDTH
with 32.
- Larry
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