On tor, 2007-07-12 at 23:36 -0700, Steven Michalske wrote:
don't use embedded nets in symbols.
now this is my opinion, but unless you have a tightly controlled
part library it will be difficult to properly.
you can also add a net attribute that will override that one I think...
don't use embedded nets in symbols.
now this is my opinion, but unless you have a tightly controlled
part library it will be difficult to properly.
you can also add a net attribute that will override that one I think...
Steve
On Jul 12, 2007, at 11:31 PM, Jonatan Åkerlind wrote:
Hi,
On Friday 13 July 2007 06:37:29 Ben Jackson wrote:
I'm looking into a bug I filed (1751566) where I found that if you:
1. select some things, then
2. hide some of them and then
3. single click in space (or on an object) to deselect all,
The hidden objects do not get deselected. This
Hi,
have a question regarding embedded power nets in symbols. I have a
design with two separate Vcc voltages (5 and 3.3 V), and one IC powered
by each. Actually the one powered by the 5V is producing the 3.3V (it's
the FTDI FT232RL USB to USART circuit) and the other is an Atmel AVR
ATTINY2313
Hi,
Is there a way to set the line capstyle from the gschem GUI? I like
thicker lines for non-net lines, and they look better with the
END_ROUND capstyle.
Is there any reason this is not the default?
Also, I'm guessing I could write a script to do this. What is the
gentlest way to get started
On Fri, Jul 13, 2007 at 08:31:20AM +0200, Jonatan ?kerlind wrote:
I've only come up with the solution to edit the 5V IC symbol and remove
the Vcc net attribute and attach a Vcc pin instead. Any other (better)
solutions?
The ultimate solution is to make all of your own symbols. There are
On fre, 2007-07-13 at 00:34 -0700, Ben Jackson wrote:
The ultimate solution is to make all of your own symbols. There are more
stylistic issues than just hiding VCC that you will run into. You will
also run into issues where there are mistakes with symbols you download
from the net, or
Jonatan,
You missed my point. One pin from the net is vissible. The other net
pins are hidden thus reducing symbol bloat.
You can have seperate nets for the core voltage, various IO voltages,
termination voltages, reference voltages etc.
But for each mostly hidden net you expose one pint.
I like partially embeded nets. Large chips, even small ones might have
several power pins which are internally connected. Rather then bloat a
symbol showing all of these pins, I like to make a embeded or hidden net
that includes all these pins and then make one of these pins visible.
The netlister
On fre, 2007-07-13 at 06:10 -0700, Steve Meier wrote:
Jonatan,
You missed my point. One pin from the net is vissible. The other net
pins are hidden thus reducing symbol bloat.
Sorry if I was unclear, actually got that point and agreed with you that
this is a good way of doing it. However,
You can force a power pin to be connected to the specified net by adding an
attribute to the IC symbol:
net=netname:pinnumber
For example if you want to connect pin 14 of U1 to +5V instead of default VCC,
add an attribute
net=+5V:14
to U1 (if it is 7400 or so, add this to all gates used on
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Hi
Here are the xpm files. Pick out what you think is the best. The only
differences are the colors of the arrow. My favourite is Place3.
These are great. I also vote for Place3.
Best regards
Tomaz
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think your post got stuck in a spam filter somewhere... forwards it to
the list since I completely agree.
Forwarded Message
From: Magnus Danielson [EMAIL PROTECTED]
To: geda-user@moria.seul.org, [EMAIL PROTECTED]
Subject: Re: gEDA-user: Separate Vcc voltages
Date: Fri, 13
On fre, 2007-07-13 at 05:04 -0700, Steve Meier wrote:
I like partially embeded nets. Large chips, even small ones might have
several power pins which are internally connected. Rather then bloat a
symbol showing all of these pins, I like to make a embeded or hidden net
that includes all these
The external net name should over ride the internel net name.
Steve M.
Jonatan Åkerlind wrote:
On fre, 2007-07-13 at 06:10 -0700, Steve Meier wrote:
Jonatan,
You missed my point. One pin from the net is vissible. The other net
pins are hidden thus reducing symbol bloat.
Sorry
On Jul 13, 2007, at 8:07 AM, Jonatan Åkerlind wrote:
On fre, 2007-07-13 at 06:10 -0700, Steve Meier wrote:
Jonatan,
You missed my point. One pin from the net is vissible. The other net
pins are hidden thus reducing symbol bloat.
Sorry if I was unclear, actually got that point and agreed
Maybe unreleased but not unavailable. Plus the ideas are always open for
use.
One idea that I have been rolling around in my brain is to drop the c
code for reading and writting the schematic files and replace it with a
scripted front end. The idea being that since there are differences
between
On Jul 13, 2007, at 9:42 AM, Jonatan Åkerlind wrote:
On fre, 2007-07-13 at 09:14 -0600, John Doty wrote:
Sorry if I was unclear, actually got that point and agreed with you
that
this is a good way of doing it. However, can the internal net
name be
Vdd or Vcc? Does the external connection
On fre, 2007-07-13 at 09:14 -0600, John Doty wrote:
Sorry if I was unclear, actually got that point and agreed with you
that
this is a good way of doing it. However, can the internal net name be
Vdd or Vcc? Does the external connection override the internal net
name?
Remember that
I agree. It goes with DJ's idea to have bus pins have multiple pin
numbers as well.
Steve Meier
On Fri, 2007-07-13 at 09:58 -0600, John Doty wrote:
On Jul 13, 2007, at 9:42 AM, Jonatan Åkerlind wrote:
On fre, 2007-07-13 at 09:14 -0600, John Doty wrote:
Sorry if I was unclear, actually got
You can force a power pin to be connected to the specified net by adding an
attribute to the IC symbol:
net=netname:pinnumber
For example if you want to connect pin 14 of U1 to +5V instead of default
VCC, add an attribute
net=+5V:14
to U1 (if it is 7400 or so, add this to all gates
I have a schematic split into multiple pages just for convenience and
ease of editing, not so much because it's hierarchical. I'd like to
use the refdes renumbering feature to generate refdeses which are
unique across all the pages, but it only seems to work that way if you
have the pages in a
i have actually used this feature myself.
from a standard release of gEDA
steve can you hook up another steve?
On Jul 13, 2007, at 8:14 AM, John Doty wrote:
On Jul 13, 2007, at 8:07 AM, Jonatan Åkerlind wrote:
On fre, 2007-07-13 at 06:10 -0700, Steve Meier wrote:
Jonatan,
You missed
On Friday 13 July 2007 18:26:09 Randall Nortman wrote:
But assuming I'm not, what is the absolute simplest way to create a
flat hierarchy?
(1) Create each page as a separate .sch file.
(2) Use the autonumbering dialog to number your parts, with refdes starting
from 100 on the first page,
I use the FTDI 232RL and RQ parts, i think they are great parts.
i use them on Mac OS X and in both there RS-232 and bit bang modes.
Steve
On Jul 13, 2007, at 12:38 AM, Jonatan Åkerlind wrote:
On fre, 2007-07-13 at 00:34 -0700, Ben Jackson wrote:
The ultimate solution is to make all of your
On Fri, Jul 13, 2007 at 01:26:09PM -0400, Randall Nortman wrote:
I have a schematic split into multiple pages just for convenience and
ease of editing, not so much because it's hierarchical. I'd like to
use the refdes renumbering feature to generate refdeses which are
unique across all the
On Fri, Jul 13, 2007 at 06:36:25PM +0100, Peter TB Brett wrote:
On Friday 13 July 2007 18:26:09 Randall Nortman wrote:
But assuming I'm not, what is the absolute simplest way to create a
flat hierarchy?
(1) Create each page as a separate .sch file.
(2) Use the autonumbering dialog
If only I'd planned this all out from the start. The problem is that
I'm taking an already completed project (schemated and layout),
snipping out part of it and adding more on.
Use the command line utility refdes_renum for this. Back up your
design first, and then fiddle with refdes_renum
For the part that's
already done, I already have refdeses assigned and matching between
schematic and layout, and I don't know of any convenient, ready-made
way to renumber a .sch and .pcb in parallel
Here are my thought on how i would do this
make a copy of the project directory
then
Steven Michalske wrote:
make a copy of the project directory
then refdes renum the whole project
now run a diff between the two, this will tell tell the old refdes
and the new refdes
craft up a script that will then do a search and replace on the pcb
file
and presto.
the
Hello,
I spent some time reading gEDA/pcb documentation in the last weeks.
Good user-documentation is very important, and I have the feeling that
gEDA/pcb documentation has made some progress in the last months.
But is it really a good idea to use much redundancy and verbosity?
Example from
But is it really a good idea to use much redundancy and verbosity?
Would you be willing to go through and fix/improve these instances of
redundancy and verbosity? Contributions to the documentation (whether
it is patches or doing it yourself via a read/write wiki account) are
always welcome
On Fri, Jul 13, 2007 at 09:22:31PM +0200, Stefan Salewski wrote:
But is it really a good idea to use much redundancy and verbosity?
Redundancy is a good idea. It can be tedious when you read a document
straight through, but it's useful when you're using the document as a
reference.
--
Ben
On Jul 13, 2007, at 1:56 PM, Ben Jackson wrote:
On Fri, Jul 13, 2007 at 09:22:31PM +0200, Stefan Salewski wrote:
But is it really a good idea to use much redundancy and verbosity?
Redundancy is a good idea. It can be tedious when you read a document
straight through, but it's useful when
People,
I'm dying here.
I'm on a critical job, pretty large, sufficient that I had to recompile
for 24 route layers. Following the re-compile, I seem to be OK for
everything until I attempt to start a route, at which point I get the
stale ratsnest message.
I've delt with this message before,
On Fri, 13 Jul 2007 08:31:20 +0200, Jonatan Åkerlind wrote:
I've only come up with the solution to edit the 5V IC symbol and remove
the Vcc net attribute and attach a Vcc pin instead. Any other (better)
solutions?
A different approach is to put the power pins into a separate symbol.
Just
* Updated my footprint library to fix a bug reported by Ben Jackson
(thanks Ben). The updated library is called Pcb_9.pm and is at
http://www.luciani.org/geda/pcb/pcb-perl-library.html
All of the example programs have been updated to call
the new library.
* Last year I posted a utility
On 7/13/07, Kai-Martin Knaak [EMAIL PROTECTED] wrote:
On Fri, 13 Jul 2007 08:31:20 +0200, Jonatan Åkerlind wrote:
I've only come up with the solution to edit the 5V IC symbol and remove
the Vcc net attribute and attach a Vcc pin instead. Any other (better)
solutions?
A different approach
On Fri, Jul 13, 2007 at 09:44:50PM -0400, John Luciani wrote:
Last year I posted a utility that reads a gschem logic symbol file
with embedded power connections and outputs a new symbol file
without the embedded power connections and a new symbol file with
only the power pins.
Maybe we
On Fri, Jul 13, 2007 at 07:40:12PM -0500, Harold D. Skank wrote:
I'm on a critical job, pretty large, sufficient that I had to recompile
for 24 route layers. Following the re-compile, I seem to be OK for
everything until I attempt to start a route, at which point I get the
stale ratsnest
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