I got the first board populated today. It works! The only ECO so far
was to increase the LED resistors for the three power monitor LEDs,
they were too bright.
http://www.delorie.com/electronics/alarmclock/
Unfortunately, Digikey put the wrong parts in the PIC24's envolope, so
I'm short two CPU
I'm glad you're finding gaf useful. I guess it must be tricky to control
a CAD package from a speech UI... please do let us know if there are any
parts of the interface which could be improved to help. Does TAB order
matter to your speech recognition software for navigation?
Actually, the mouse op
On Sat, 2007-09-08 at 17:12 -0400, Robert Butts wrote:
> > U, is there any reason you are trying to SPICE simulate
> a circuit
> > with a relay in it? SPICE doesn't have exactly the concept
> of a
> > relay, and won't know what to do with it when trying
> U, is there any reason you are trying to SPICE simulate a circuit
> with a relay in it? SPICE doesn't have exactly the concept of a
> relay, and won't know what to do with it when trying to simulate.
>
> SPICE thinks that an S refdes is a voltage controlled switch:
I'm disabled and use spee
On Sep 7, 2007, at 8:06 PM, al davis wrote:
> On Thursday 06 September 2007, Larry Doolittle wrote:
>> PCB can't do the automated parasitic extraction and signal
>> integrity simulations that high end software suites can.
>
> Actually, a first cut, without crosstalk, is fairly easy to do.
> First,
Ah... I thought it was a brand new checkout but I must have checked out a
version
long long time ago under my project directory. That's why I had the problem.
I deleted that directory and checkout again. It worked.
(I feel like an idiot)
Andy
On 9/8/07, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
>
On Sat, Sep 08, 2007 at 08:36:17AM -0500, Harold D. Skank wrote:
>
> What I find is that frequently when I start a job (most recently miter),
> the job starts OK, then the monitor shows that memory consumption starts
> to grow until I see of the order of 99.0-99.5% memory commitment.
I've seen PC
On Sat, 2007-09-08 at 12:36 -0400, Andy Fong wrote:
> I followed the instruction on the sourceforge page to check out the
> latest from CVS.
>
> After check out, a lot of files has unresolved conflicts and even
> modification not commited yet as shown by "cvs -n update".
> (I don't think this is
If you have uncommitted modifications, that means that your *local*
tree had them. Check out into an empty directory.
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I followed the instruction on the sourceforge page to check out the latest
from CVS.
After check out, a lot of files has unresolved conflicts and even
modification not commited yet as shown by "cvs -n update".
(I don't think this is even possible with CVS. Something must be seriously
wrong.)
Here
> What I find is that frequently when I start a job (most recently miter),
> the job starts OK, then the monitor shows that memory consumption starts
> to grow until I see of the order of 99.0-99.5% memory commitment.
Any messages in the console? Like, warnings about a big undo buffer?
___
al davis wrote:
> On Thursday 06 September 2007, Larry Doolittle wrote:
>> PCB can't do the automated parasitic extraction and signal
>> integrity simulations that high end software suites can.
>
> Actually, a first cut, without crosstalk, is fairly easy to do.
> First, we need a translator, to
On Saturday 08 September 2007, Harold D. Skank wrote:
> I need to emphasize that I have my machine loaded to maximum
> memory capacity. Can anyone suggest a rationale short of a
> different machine that I might be able to use to improve
> machine performance?
I haven't tried this, but here's a th
People,
I'm having a pretty tough time here. I have a design using a Xilinx
Vertex-5 part with over 1100 pins. Other connectors have over 200 pins
as well, with 431 lines in the netlist file, and 14 to 16 layers.
My system is running Fedora-7, and the latest gEDA release (I think).
Specifically
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