Peter Baxendale wrote:
Hi gerbv people,
Just posted a gerbv 2.0.0 feature to the gerbv bug tracker. Working
with a reference design from Nordic Semiconductor I found that gerbv
wasn't showing some bits around the antenna correctly (ie as shown in
the Nordic documentation). Stripped it down
Wow, that was quick! Hate to think what that kind of service would cost
commercially. Many thanks!
On Thu, 2008-01-24 at 10:59 +0100, Stefan Petersen wrote:
Peter Baxendale wrote:
Hi gerbv people,
Just posted a gerbv 2.0.0 feature to the gerbv bug tracker. Working
with a reference
Hi again!
BTW I forgot to ask, is it possible to determine which CAD program that
has been used to generate these gerber files? It usually says in the top
of the file after some G04 remark command.
Regards,
/Stefan
Peter Baxendale wrote:
Wow, that was quick! Hate to think what that kind of
Hi, I've got two related questions pertaining to connecting nets.
Q1: Is there a way to apply one net name to a group of selected net
segments? Presently, I'm 2x-clicking each segment to edit, then pasting
netname, hitting enter twice to apply the setting...
Q2: Is there a way to select all net
Unfortunately there's nothing in the gerbers to indicate where they came
from. The schematic (a pdf) has a reference to Protel in it, which may
or may not be a clue.
On Thu, 2008-01-24 at 15:30 +0100, Stefan Petersen wrote:
Hi again!
BTW I forgot to ask, is it possible to determine which CAD
Günter Dannoritzer wrote:
Hi,
I am looking into using Icarus Verilog with Teal/Truss, a C++ based
verification framework.
With Icarus 0.8.6 all tests but the last, with release of a_wire, are
working.
It's probably a matter of it not being implemented yet. Looks like
a candidate for a bug
epswint wrote:
Q1: Is there a way to apply one net name to a group of selected net
segments?
[jg] I don't know one.
Presently, I'm 2x-clicking each segment to edit, then pasting
netname, hitting enter twice to apply the setting...
[jg] Instead you can get better use of time by copying a
To set a net's name you only need to add the net=this_net_name to one
segment of a group of connected net segments.
gnetlist is smart enough that it will name the entire group of connected
net segments.
If you have two non-connected net segments that you want to be on the
same net then each
How does one use the ~/.pcb/colors/Default file?
I have not found how to get pcb to use .Xdefaults or the ~/.pcb/colors/Default
file.
I used to have some different colors defined and no more..
A recent compile and install did not create this dir after I moved it away as
an experiment...
John Griessen wrote:
I have not found how to get pcb to use .Xdefaults or the
~/.pcb/colors/Default file.
This part I found out and is answered. I made changes to .Xdefaults and then
did
xrdb -merge .Xdefaults
to get colors to change.
Still interested to know about the
I have not found how to get pcb to use .Xdefaults or the
~/.pcb/colors/Default file.
.Xdefaults: (lesstif only):
Pcb.layer-color-1: #b15810
Pcb.layer-color-2: #008000
Pcb.layer-color-3: #aa
Pcb.layer-color-4: #9401b9
Pcb.layer-color-5: #3000a0
Pcb.layer-color-6:
On Thu, 2008-01-24 at 14:17 -0800, Steve Meier wrote:
To set a net's name you only need to add the net=this_net_name to one
segment of a group of connected net segments.
Make that netname= for an attribute attached to a net.
The names are a little confusing. net=foo:1 is used to attach to
On Thu, 24 Jan 2008 18:50:20 -0500, DJ Delorie wrote:
The .pcb/colors/Default is gtk only.
contents of my .pcb/colors/Default:
/
black-color = #00
white-color = #ff
background-color = #ff
crosshair-color = #ff
cross-color = #00
via-color
yep.. good catch Peter
Steve M.
On Fri, 2008-01-25 at 00:39 +, Peter Clifton wrote:
On Thu, 2008-01-24 at 14:17 -0800, Steve Meier wrote:
To set a net's name you only need to add the net=this_net_name to one
segment of a group of connected net segments.
Make that netname= for an
Thanks for all the tips. I will miss being able to select a segment,
right-click, and choose select entire net. It makes browsing a new
design (or digging up an old one) a lot easier... Well, I might add
that in once I've gotten familiar with the code ;)
Steve Meier wrote:
yep.. good
Question:
Does *anybody* use or even see value in the 32bit runtime support
that Icarus Verilog includes in 64bit builds? In particular, there
is support in the Icarus Verilog source for building simultaneously
a vvp (64bit) and a vvp32 (32bit) to support 32bit VPI's transported
from 32bit
Steve -
On Thu, Jan 24, 2008 at 09:03:39PM -0800, Stephen Williams wrote:
Does *anybody* use or even see value in the 32bit runtime support
that Icarus Verilog includes in 64bit builds?
Not purists like me, that have everything built from source
on any given platform. The interest would
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