Dear all,
Has any one of you designed a PCB with a 144 pin
QFP/TQFP package ? (with or without exposed die pad)
If so, is one of you so kind to show me the PCB files
?
How many layers will such a board have ?
Until recently i designed boards with a max of 44 (ic)
pins. So i do not feel
On Fri, 01 Feb 2008 21:48:26 -0500
Dan McMahill [EMAIL PROTECTED] wrote:
I've placed a new pcb snapshot up on sourceforge. In addition to the
usual source release, there is an installer for windows. Be warned that
the windows build has received very little testing.
The windows build works
Simon,
Get your confidence up 144 pin qfp is very standard.
Layers.
Maybe 3 for power and ground (Vcci, Vccio and ground)
3 for signals Top, bottom and one in the middle.
Even if you need analog then you can either add a few more layers or
carefully manage the layers that you have.
i.e if
On Feb 2, 2008, at 7:09 AM, ST de Feber wrote:
Has any one of you designed a PCB with a 144 pin
QFP/TQFP package ? (with or without exposed die pad)
If so, is one of you so kind to show me the PCB files
?
How many layers will such a board have ?
Until recently i designed boards with a max
I installed the gnucap that was listed in the fedora 7 package manager. The
version is 0.35 and when I start gnucap I see this warning:
Never trust any version less than 1.0
What's up with this, do I need to update it and if so is this done with: rpm
-u?
On Saturday 02 February 2008, Robert Butts wrote:
Never trust any version less than 1.0
If you design a new chip, and spend $10 million to get it made,
and it doesn't sell ... It's not my fault.
___
geda-user mailing list
geda-user@moria.seul.org
If it a microsoft application it won't even function until at least 3.1
al davis wrote:
On Saturday 02 February 2008, Robert Butts wrote:
Never trust any version less than 1.0
If you design a new chip, and spend $10 million to get it made,
and it doesn't sell ... It's not my
Nearly every major part I need for my latest project is packaged in a QFN
(or LFCSP as they call it over at Analog Devices). I'm worried because the
parts have round leads and Sunstone, the PCB prototype shop, says they can't
make radiused SMD pads. Has anyone run into trouble with this, or are
Seriously, why the warning?
On Feb 2, 2008 2:09 PM, Steve Meier [EMAIL PROTECTED] wrote:
If it a microsoft application it won't even function until at least 3.1
al davis wrote:
On Saturday 02 February 2008, Robert Butts wrote:
Never trust any version less than 1.0
If you design a
On Feb 2, 2008 11:23 AM, Jeffrey Baker [EMAIL PROTECTED] wrote:
Nearly every major part I need for my latest project is packaged in a QFN
(or LFCSP as they call it over at Analog Devices). I'm worried because the
parts have round leads and Sunstone, the PCB prototype shop, says they can't
The shop I use insists that the solder mask features must be at least 5
mills wide other wise you should gang unmask the pads.
Steve Meier
joe tarantino wrote:
On Feb 2, 2008 11:23 AM, Jeffrey Baker [EMAIL PROTECTED]
mailto:[EMAIL PROTECTED] wrote:
Nearly every major part I need for my
I've finished entering a schematic and have started laying out the foil
with pcb. I found that Vdd got connected to Vcc sometime during the
schematic entry. Short of poring over the entire schematic, how can I
find where this happens?
--
David Griffith
[EMAIL PROTECTED]
A: Because it fouls
On Saturday 02 February 2008, Robert Butts wrote:
Seriously, why the warning?
To make it legal in California.
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
On Sat, Feb 02, 2008 at 12:09:37PM +, ST de Feber wrote:
Has any one of you designed a PCB with a 144 pin
QFP/TQFP package ? (with or without exposed die pad)
I just made a board with a QFP208 (0.5mm), 100 (0.65mm rectangular) and
80 (0.65mm square).
How many layers will such a board
I have a design with two subcircuits. I pretty much copied the gTAG
example but I missed the trick of making a netname=foo wire in the
toplevel and then putting an input or output with refdes=foo in the
subdesigns, so my +3.3V isn't continuous through my board as intended.
The odd thing is that
David Griffith wrote:
I found that Vdd got connected to Vcc sometime during the
schematic entry. Short of poring over the entire schematic, how can I
find where this happens?
You can cut apart nets and rerun gnetlist if you must stay in graphical
mode...errr no,
there's no higlightin in
On Sat, 2 Feb 2008, John Griessen wrote:
David Griffith wrote:
I found that Vdd got connected to Vcc sometime during the
schematic entry. Short of poring over the entire schematic, how can I
find where this happens?
You can cut apart nets and rerun gnetlist if you must stay in
17 matches
Mail list logo
