Can either of these simulators handle an encrytped model? I have some from
fairchild that are hspice format, using .prot FREELIB , which is
encrypted.div
gene
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Can either of these simulators handle an encrytped model? ?I have
some from fairchild that are hspice format, using .prot FREELIB ,
which is encrypted.
The short answer is no.
To expound on this answer, if the HSpice folks were to release details
about their encryption algorithm, then we could
At 09:49 AM 4/25/2008, you wrote:
Can either of these simulators handle an encrytped model? I have
some from fairchild that are hspice format, using .prot FREELIB ,
which is encrypted.
The short answer is no.
To expound on this answer, if the HSpice folks were to release details
about their
* Try turning of the pads and see if there is a small amount amount of
copper under the pad.
* Are your traces and pads on the same side of the board?
* Can you connect with with auto enforce DRC clearance off?
Hi John,
The last suggestion enabled me to connect to the pad. I guess that
Q1) I guess that Clearance/2 means enter 2 to get 0.1 hipot clearance?
Clearance is an amount added to the *diameter* of the pins/pads, so
yes, 200 mil clearance gives 100 mil copper gap.
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On Fri, 2008-04-25 at 00:49 +, Kai-Martin Knaak wrote:
On Tue, 22 Apr 2008 11:30:35 +0100, Peter Clifton wrote:
Another way being investigated was using new arbitrary user font
support being developed for cairo, to cache rendered glyphs and speed
things up.
This seems to me the
On Fri, Apr 25, 2008 at 10:24 AM, Ian Chapman [EMAIL PROTECTED] wrote:
* Try turning of the pads and see if there is a small amount amount of
copper under the pad.
* Are your traces and pads on the same side of the board?
* Can you connect with with auto enforce DRC clearance off?
Hi
Hi John, I was using skinny traces for experimenting set to 5 mils width and
spacing. Other than that I am using the defaults. I'll have to read on the
docs to determine how to change the DRC?
On Fri, Apr 25, 2008 at 10:24 AM, Ian Chapman [EMAIL PROTECTED] wrote:
* Try turning of the pads
On Fri, Apr 25, 2008 at 12:14 PM, Ian Chapman [EMAIL PROTECTED] wrote:
Hi John, I was using skinny traces for experimenting set to 5 mils width and
spacing. Other than that I am using the defaults. I'll have to read on the
docs to determine how to change the DRC?
EMACS ;-)
I look for the
In my # release: pcb 20080202 version I have:-
DRC[2000 1000 2000 1000 1500 1000] and since they are in square brackets
that works out to be 0.020 spacing and that's fine for through hole but not
so good for TQFP with 0.5mm pad spacing. I'll change the PCB file to 5 or
10 mil if there is not a
There is a GUI option. For GTK, it's in file-preferences, in the
lesstif version it's edit-board sizes.
Clearance should depend on your board fab's design rules. For 8 mil
spacing for example, you need 8 mil gap as well (it's spacing after
all), so set your clearance accordingly.
On Fri, Apr 25, 2008 at 1:18 PM, Ian Chapman [EMAIL PROTECTED] wrote:
In my # release: pcb 20080202 version I have:-
DRC[2000 1000 2000 1000 1500 1000] and since they are in square brackets
that works out to be 0.020 spacing and that's fine for through hole but not
so good for TQFP with
Bummer :(
Fairchild offers some on-line tools for selecting and testing mosfet (and some
other stuff as well). Problem is, it's not my circuit and does not show what I
am looking for. I'm interested in THD performance of my entire circuit -
something they can't provide. I don't have the
I just completed a couple of boards using the 100 pin TQFP and I used
6/6 (0.165/0.165 mm actually) on one board which needed fine pitch to
be routable and 10/10 on the other. The fine pitch board had a lot
more 0.635 mm pitch parts which the smaller grid was compatible
with. It was no real
I just completed a couple of boards using the 100 pin TQFP and I used
6/6 (0.165/0.165 mm actually) on one board which needed fine pitch to
be routable and 10/10 on the other. The fine pitch board had a lot
more 0.635 mm pitch parts which the smaller grid was compatible
with. It was no real
I use FreePCB which will always align the first trace with the pin
and puts the second vertex on grid. Does PCB do that as well, or do
you have to switch grids?
PCB has snap-to-pin and automatic two-part traces, so as long as you
start or end on the pad's snap point, it aligns the traces for
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
As you know, this year's Icarus Verilog GSoC candidate is working
on a VHDL code generator back-end for Icarus Verilog. Hooray!
But suddenly the obvious question comes up, How are we going to
run these generated files? I'm here looking for
On Fri, 25 Apr 2008 14:04:38 -0700
Stephen Williams [EMAIL PROTECTED] wrote:
As you know, this year's Icarus Verilog GSoC candidate is working
on a VHDL code generator back-end for Icarus Verilog. Hooray!
But suddenly the obvious question comes up, How are we going to
run these generated
On Friday 25 April 2008, Stephen Williams wrote:
As you know, this year's Icarus Verilog GSoC candidate is
working on a VHDL code generator back-end for Icarus Verilog.
Hooray! But suddenly the obvious question comes up, How are
we going to run these generated files? I'm here looking for
Rick Collins wrote:
a footprint. In the past I have found pre-designed libraries to be
unreliable. So I create my own footprints from scratch... well not
quite from scratch.
I have found the same thing. I've made slow progress at improving the
pcb libraries, but it is slow and tedious.
[EMAIL PROTECTED] wrote:
Can either of these simulators handle an encrytped model? I have some
from fairchild that are hspice format, using .prot FREELIB , which is
encrypted.
I'd be surprised. It seems to me that if you knew how to use the
encrypted models then you'd also know how to
On Friday 25 April 2008, Dan McMahill wrote:
[EMAIL PROTECTED] wrote:
Can either of these simulators handle an encrytped model?
I have some from fairchild that are hspice format, using
.prot FREELIB , which is encrypted.
I'd be surprised. It seems to me that if you knew how to use
the
* Corrected the silkscreen body on AMP 102979 and 103149 series
connectors. The outside edge of the body is 140mils from the center
of the first pin row. I mistakenly set the inside edge of the body
to 140mils from the center of the first pin row.
* Added footprint for solder jumpers
On Fri, 25 Apr 2008 15:29:06 -0400, DJ Delorie wrote:
PCB has snap-to-pin and automatic two-part traces, so as long as you
start or end on the pad's snap point, it aligns the traces for you.
Check, the option Crosshair snaps to pins and pads in the settings menu
Insert can be set to snap
On Fri, 25 Apr 2008 16:01:28 +0100, Peter Clifton wrote:
Any prediction how long I should hold my breath? Months? Years?
http://cairographics.org/roadmap/
November 2008 is suggested, but the support isn't merged yet.
Ok. So I'll ask again in spring 09 ;-)
---(kaimartin)---
--
Kai-Martin
I'm okay now, I set it to 0.008, thanks for all the help. I am
planning to use http://www.4pcb.com/ Advanced Circuit's 4 layer, 30 sq
ins, 66$ special and they use 0.006 line/space unless any one has had a
bad experience with them? They were fine on a low tech two layer
through hole board.
On Fri, Apr 25, 2008 at 10:08 PM, Ian Chapman [EMAIL PROTECTED] wrote:
I'm okay now, I set it to 0.008, thanks for all the help. I am
planning to use http://www.4pcb.com/ Advanced Circuit's 4 layer, 30 sq
ins, 66$ special and they use 0.006 line/space unless any one has had a
bad
I am planning to use http://www.4pcb.com/ Advanced Circuit's 4
layer, 30 sq ins, 66$ special and they use 0.006 line/space unless
any one has had a bad experience with them? They were fine on a low
tech two layer through hole board.
I used the $66 special for my latest furnace board, it's
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