One of these days we should just switch to the resource file format
and be done with it. Then you could fairly easily (I think) let the
current default units basically be set as you go down a tree.
I still have layer types megapatch and blind/buried vias on my
plate too, I'll probably do
Now, of course, old lex/yacc hands will point out that this kind of
communication is dangerous, since the parser looks ahead,
The parser looks ahead to scan tokens, which means you need to
recognize all the tokens in the parser, not half in the parser and
half in the lexer. It will reduce
?? which is what?
The format we use for pcb-menu.res and gpcb-menu.res. It's a
heirarchical text format with tagging and grouping. Semantically,
it's like XML, but without all the heavy baggage that comes with XML.
It allows forward compatibility and third-party expansion, is easy to
parse,
On Sun, May 25, 2008 at 4:25 AM, Rick Collins [EMAIL PROTECTED] wrote:
Or perhaps the software should check this and give a warning when
placing a part so that it is not connectable.
It could be cute to have a libgsymcheck which gschem's component
selector could invoke each time you select a
Hi Bernd,
On Mittwoch, 11. Juni 2008, Bernd Jendrissek wrote:
On Sun, May 25, 2008 at 4:25 AM, Rick Collins [EMAIL PROTECTED]
wrote:
Or perhaps the software should check this and give a warning when
placing a part so that it is not connectable.
It could be cute to have a libgsymcheck
Hi DJ,
On Wed, 2008-06-11 at 11:32 -0400, DJ Delorie wrote:
?? which is what?
The format we use for pcb-menu.res and gpcb-menu.res. It's a
heirarchical text format with tagging and grouping. Semantically,
it's like XML, but without all the heavy baggage that comes with XML.
It allows
# maybe we have an author with licensing issues ?
author = me, myself and I
use-license =unlimited2 ;-)
dist-license = LGPL
Well, we could carry forth the Attribute list:
attributes = (
author = foo
license = ...
)
but really, you could add new
I've just created a pcb footprint, but gsch2pcb can't find it.
I get the error message
1 elements could not be found.
And -v -v shows:
Searching: packages/custom symbols for CVEXTCONN-1
: SIM-1.sym No
: SIM-1.sym~ No
:
1. file suffixes aren't magic. If it's looking for CVEXTCONN-1 there
needs to be a file called CVEXTCONN-1 available.
2. *.sym are gschem symbols. PCB uses *.fp footprints.
___
geda-user mailing list
geda-user@moria.seul.org
DJ Delorie schrieb:
1. file suffixes aren't magic. If it's looking for CVEXTCONN-1 there
needs to be a file called CVEXTCONN-1 available.
2. *.sym are gschem symbols. PCB uses *.fp footprints.
Sorry, I confused the name of the pcb footprint and the geda symbol.
It's working now.
For the curious, I just populated two of the three first boards:
http://www.delorie.com/pcb/docs/gs/firstboards.html
Yes, they both work (that was the whole idea behind making them - make
sure the docs teach you something that works :)
Still waiting for the four-layer board from batchpcb.
On Thu, Jun 12, 2008 at 12:40:42AM -0400, DJ Delorie wrote:
For the curious, I just populated two of the three first boards:
It would help if you put width/height tags on your imgs because otherwise
the page continues to re-lay-out over and over as the images load in.
(referring to the gs
While I've found the autorouter to take some time in the past I now have
a problem where it doesn't seem to complete at all, resulting in a
program hang. The board isn't very complex, the autorouter doesn't
complete in 7 hours on a Core 2 Duo running at 1.2 Ghz.
Philipp
bar.pcb
Description:
13 matches
Mail list logo
