DJ Delorie wrote:
Perhaps if the netlist used symbolic names (pin names in pcb) instead
of pin numbers, and added a pin-swap list? Then pcb could swap the
symbolic names and everything else just works.
That sounds like a good way to define a netlist. Has Steve Meier
already tested this
Ben == Ben Jackson [EMAIL PROTECTED] writes:
On Sun, Sep 28, 2008 at 12:49:45PM +0200, David Kuehling wrote:
Unfortunately, flooding 0603 components results in a thin copper
hair in between the pads, that is less than 6 mil and thus violates
design rules.
Stefan Salewski [EMAIL PROTECTED] writes:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability—on the noninvert-
ing input, it can react with the source impedance to cause
There appears to be an error in the centroid calculation in
pcb-20080202. If I load the pcb (below) in version pcb-20050315 and
output the xy data I get
C1,0805,0.1u,700.00,325.00,0,bottom
when I output xy data with pcb-20080202 (both lesstif and gtk)
I get
C1,0805,0.1u,700.00,529.00,0,bottom
On Mon, 2008-09-29 at 09:13 -0400, John Luciani wrote:
There appears to be an error in the centroid calculation in
pcb-20080202. If I load the pcb (below) in version pcb-20050315 and
output the xy data I get
C1,0805,0.1u,700.00,325.00,0,bottom
Is that the stock 0805 footprint, or your own?
On Mon, 2008-09-29 at 09:35 -0400, John Luciani wrote:
On Mon, Sep 29, 2008 at 9:28 AM, Peter Clifton [EMAIL PROTECTED] wrote:
On Mon, 2008-09-29 at 09:13 -0400, John Luciani wrote:
Is that the stock 0805 footprint, or your own?
My own.
Just wondering.. I have a lot of 0805 parts
On Mon, 2008-09-29 at 15:01 +0100, Peter Clifton wrote:
On Mon, 2008-09-29 at 09:35 -0400, John Luciani wrote:
Does your XY data look correct for your 0805 parts?
It seems to be correct in gerbv, although I have never figured out how
gerbv seems to guess the size of component box it
Hmm, let's do some math:
Board size: Xpcb = 184200, Ypcb = 85400 [mil/100].
C1 is on: Xcomp = 700, Ycomp = 325 [mil]
Centroid XY coords: X = Xcomp, Y = Ypcb - Ycomp = 854 -325 = 529 [mil]
Hmm, version 20080202 looks good to me.
Where are your origins ?
IIRC, Dan did explain this one (and
IIRC board coordinates are measured from the upper left
so board size should have no affect on the centroid coordinates
within my board.
If I center the crosshair in the center of the 0805 (which is the
centroid for this package) both versions of PCB display
the value (700,325). When the xy data
On Mon, Sep 29, 2008 at 05:42:58PM +0200, Bernd Jendrissek wrote:
I can still see how to do this fairly easily for swaps of equivalent
inputs on the same functional unit / slot, but could one extend such a
pin-swap database to handle swapping of whole slots at a time?
I can think of several
Hi John,
In my git-ified pcb repo I have:
quote
Author: danmc danmc
Date: 01/03/2008 12:45:12 AM
Parent: change the preprocessor logic a bit to avoid #ifdef-ing i...
Child: apply patch 1852864 GTK HID: scrolled layer preferences
Branch: master (Display nets as a hierarchical tree in the netlist
Program name: convert_sym
Written by: Mike Jarabek
convert_sym takes ViewLogic Viewdraw schematic or symbol and outputs a
gschem compatible file. This utility should be considered a work in
progress. Be warned, this program has quite a few limitations. See the
README file in the utils/ directory
Kipton Moravec wrote:
Program name: convert_sym
Written by: Mike Jarabek
convert_sym takes ViewLogic Viewdraw schematic or symbol and outputs a
gschem compatible file. This utility should be considered a work in
progress. Be warned, this program has quite a few limitations. See the
README
Thanks for the quick response. I will let you know how it goes. I have
13 years of schematics to convert.
Kip
On Mon, 2008-09-29 at 19:19 -0400, Mike Jarabek wrote:
Kipton Moravec wrote:
Program name: convert_sym
Written by: Mike Jarabek
convert_sym takes ViewLogic Viewdraw schematic or
Fixed. The problem wasn't that the pads disappeared, they were
created on the wrong layer. I checked in the attached patch, give it
a try.
Index: buffer.c
===
RCS file: /cvsroot/pcb/pcb/src/buffer.c,v
retrieving revision 1.45
diff
At 07:06 PM 9/28/2008, you wrote:
I guess I am thinking in terms of having partially routed a net and
found that to continue, it is better to swap a pin at the unrouted
end. Are you saying that you can see the problem without routing?
Yes, sometimes. For example, running 24 chip select
On Mon, 2008-09-29 at 19:19 -0400, Mike Jarabek wrote:
Kipton Moravec wrote:
You can use this program on the Viewdraw schematics, and all symbol
files, running it should give a brief command line synopsis. When you
set up your geda project, I would recommend putting the schematics in
one
If you just update the schematic and import the new net list,
doesn't that cause the trace for that net to be ripped up?
It doesn't rip it up, but it does show up as a short.
And how is that then fixed?
It's not fixed. You still have to edit the board to make it match the
netlist;
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