Yes, I made a change which affected http git access. I have
re-enabled git access via http. Please try again.
Cloning gaf.git works OK, but cloning pcb.git gives the same error
gar...@xdcnb047-vbox:~/devel/geda$ git clone http://git.gpleda.org/pcb.git
Initialized empty Git repository in
Hello,
What am I missing ?
On the component side I only have ground tracks and one additional one.
To make a ground plan, I use rectangle, unfortunately, doing so, I
get copper every where, ie. the spacing aroud the pins is OK but the
track which is not supposed to be grounded is connected to
[snip]
Cloning gaf.git works OK, but cloning pcb.git gives the same error
gar...@xdcnb047-vbox:~/devel/geda$ git clone http://git.gpleda.org/pcb.git
Is this the right URL? I thought it was supposed to be
http://git.gpleda.org/git/pcb.git. Please check the gaf.git URL and
see if it has a
Is this the right URL? I thought it was supposed to be
http://git.gpleda.org/git/pcb.git. Please check the gaf.git URL and
see if it has a .../git/... in there.
-Ales
Aaaah, that's it, thanks Ales. I must have being doing a pull on an
existing repo rather than a new clone of the gaf repo.
You need to make sure that the traces have the attribute clearpoly. I
usually do a search and replace in a text editor; I'm not sure if
there's a shortcut in PCB that let's you process traces already placed.
Under the Settings menu there is an option New lines, arcs, clear
polygons that will
On Tue, Feb 10, 2009 at 08:44:15AM -0500, Ethan Swint wrote:
You need to make sure that the traces have the attribute clearpoly. I
usually do a search and replace in a text editor; I'm not sure if
there's a shortcut in PCB that let's you process traces already placed.
It's typically the J
Thank you very much.
You need to make sure that the traces have the attribute clearpoly. I
usually do a search and replace in a text editor; I'm not sure if
there's a shortcut in PCB that let's you process traces already placed.
Under the Settings menu there is an option New lines, arcs,
Paul Tan wrote:
Hi John,
There is a BASH script geda_hier_tools.bsh to generate
Hierarchical Verilog netlist
Thanks Paul,
I'm wanting to get things going in an easy to maintain way with as few steps
as possible. I'd like to do it in scheme, from one launch of gnetlist, if
possible.
Then
Gabriel Paubert wrote:
Under the Settings menu there is an option New lines, arcs, clear
polygons that will make sure that any additional lines you place will
not be merged into a polygon.
This very same behavior tripped me up on my first board with PCB. Is
there some reason that New
Is there some reason that New Lines... clear polygons is not on by
default?
It *is* on by default. The problem is that gsch2pcb doesn't use pcb's
defaults. That's why in my tutorials, I don't let gsch2pcb create the
initial board.
___
geda-user
DJ Delorie wrote:
Is there some reason that New Lines... clear polygons is not on by
default?
It *is* on by default. The problem is that gsch2pcb doesn't use pcb's
defaults. That's why in my tutorials, I don't let gsch2pcb create the
initial board.
Ah... well, then I dereference the
Dave N6NZ wrote:
Is there some reason that New Lines... clear polygons is not
set by default by gsch2pcb? It would seem to violate the principal of
least surprise.
DJ's mentioned this before. There's a thought or two going on about that.
A new version of gschem--PCB flow could drive pcb
Ah... well, then I dereference the pointer and ask the question of
gsch2pcb: Is there some reason that New Lines... clear polygons is not
set by default by gsch2pcb? It would seem to violate the principal of
least surprise.
I could be mistaken, but I think the newer repo versions of gsch2pcb
In my gafrc file in the current directory, I have the line:
(paper-size 17.0 11.0) ; tabloid
However, this is ignored by gschem even though the status window
reports read local gafrc. This behavior turned up in 20081231 from
Fedora 10, but was ok in 20081220 from Fedora 8.
Any ideas? Its not
Am Dienstag, den 10.02.2009, 12:06 -0800 schrieb Matt Ettus:
In my gafrc file in the current directory, I have the line:
(paper-size 17.0 11.0) ; tabloid
For gEDA we have gafrc and gschemrc.
Paper size seems to be more related to gschem direct.
Indeed, in /usr/share/gEDA/system-gschemrc I
Thanks! That fixed it.
Matt
On Tue, Feb 10, 2009 at 1:32 PM, Stefan Salewski m...@ssalewski.de wrote:
Am Dienstag, den 10.02.2009, 12:06 -0800 schrieb Matt Ettus:
In my gafrc file in the current directory, I have the line:
(paper-size 17.0 11.0) ; tabloid
For gEDA we have gafrc and
**HINT HINT... I WANT FEEDBACK ON THIS BRANCH ...HINT HINT**
Now would be the time to grab a copy of the PCB+GL before_pours
branch, and have a play to see how it impacts performance on your
polygon-intensive board layouts.
git clone git://repo.or.cz/geda-pcb/pcjc2.git
git checkout -b
Matt Ettus wrote:
In some Xilinx models, they make instantiations like this:
block instance(ports);
defparam instance.param=VALUE
This normally works ok. The problem is that inside the block,
generate statements are being used which are dependent on the value of
the parameter. What
John Griessen wrote:
This is probably a Mike Jarabek question:
Could be... Sorry for the delay, got swamped.
I don't get usable hierarchic netlist output when I have placed schematics
and use the gnet-verilog.scm back-end.
It drops the module definitions and endmodule statements of the
Hi,
I don't want to export the entire part of my schematic into a EPS
image, especially the right bottom part. How can I make it?
I remember that I could do it a long time ago, around 2005. When I
exported the schematic, I only exported the central part with parts
and nets
I made a foo.sch with lots of symbols. The .sym file has a 'source='
attribute and for good measure so does each instance of the symbol.
The sub.sch is in the same directory. I have a gafrc:
(source-library .)
In gschem my symbols appear. I can go 'down' into the symbol. I can go
'down' into
Hi Peter and all,
Peter Clifton wrote:
For those testing the PCB+GL branch
git clone git://repo.or.cz/geda-pcb/pcjc2.git
git checkout -b before_pours origin/before_pours
And to update (easiest I think.. but discards local changes):
git fetch
git checkout master
git branch -D
On Sun, Feb 8, 2009 at 1:13 PM, al davis ad...@freeelectron.net wrote:
On Sunday 08 February 2009, Christoph Lechner wrote:
How can it know?
Well, I thought: maybe there's some attribute dedicated to
this case ...
The Spice netlister is loaded with special cases, because the
Spice syntax
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