> DJ is just looking for the best way to solve his design problem.
I think what I'll do is leave the chip where it is, and add what
serpentines I can to the shorter traces. I'll leave in the LA
connector but solder in the via wires in such a way that I can remove
them later - that way, I can deb
Hi Steven,
I thought your rule of thumb and mine were nearly the same, actually.
Let's just drop the math out of it. Leave it as an exercise for student
to run a spice simulation (or hyperlinx if you have it) and see for
themselves :)
If you want to ask the heavy-weights on this matter, the S
I use feed-through wires. Usually I strip down some 22ga stranded
speaker wire and use the strands. They fit in 13 mil holes very
nicely :-)
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Hi DJ, loved your CC article and can't wait to see your next one.
On Mon April 6 2009 11:36:38 pm DJ Delorie wrote:
> > Do you have the other side of your board to route on? Maybe that would
> > help.
>
> I do, but I have to manually solder in every single via. My vias are
> small, but not *tha
On Sun April 5 2009 05:34:44 pm Peter Clifton wrote:
> On Sun, 2009-04-05 at 16:49 -0400, Mark wrote:
> > Now I have a working DRC-GUI using master from the repo but it still
> > causes PCB to crash when I use the settings for Thin Draw or Thin Draw
> > Poly.
> >
> > Hopefully that will help to nar
On Tue, 2009-04-07 at 15:12 -0600, Miles Gazic wrote:
> I have attributes in my symbol files that I mark as "visible". This
>makes them visible when editing the .sym file, but NOT when editing
>the .sch file.
I don't think so. I think if I add visible attributes to a symbol, they
are vis
I have attributes in my symbol files that I mark as "visible". This
makes them visible when editing the .sym file, but NOT when editing
the .sch file. I do not want them "promoted" (which I think will copy
the text of them to the contents of my .sch files, when a symbol is
inserte
Guys:
I just started using the SOT26 footprint, and noticed that the reference
designator i.e. "U1" is located directly on top of pin 4 instead of near
pin 1.
Obviously, I can move the reference designator to anywhere I want :),
but I'm just wondering if that's the way things are intended to
On Apr 7, 2009, at 10:48 AM, [1]carzr...@optonline.net wrote:
- Original Message -
From: John Griessen
[jg]I think HJ might have meant length of the ramp up or ramp
down when he said "edge".
I can't see how length of a square wave half cycle translates
to
The simulated annealing or however it's called sometimes
> produces awful placements (and I had less than 1% of the chip
> used, an XC3S200A-FT256). Floorplanning can help a lot
> in these cases.
>
> Gabriel
I would refrain from floorplanning on small designs. Are you using a
constraints
- Original Message -
From: John Griessen
> [jg]I think HJ might have meant length of the ramp up or ramp
> down when he said "edge".
> I can't see how length of a square wave half cycle translates
> to fractions of wavelengths at some resonance...which is where "1/4 *
> 'lengt
On Mon, Apr 06, 2009 at 10:41:57PM -0400, DJ Delorie wrote:
>
> > That could work too. But, honestly, from what I see on your board
> > what's the problem besides the stubs?
>
> If I knew that answer, I wouldn't need to ask all these questions.
>
> > Oh, and make sure to set the constraints on y
On Mon, Apr 06, 2009 at 12:04:18PM -0500, John Griessen wrote:
> Larry Doolittle wrote:
> I have
> > done it on Debian, but the details are not distribution-specific.
> > The biggest hack is bypassing the stoopid shell scripts that
> > autodetect architecture and figure out which version to install
gene glick wrote:
> Steven Michalske wrote:
>
> Hey Steven, that's a pretty interesting analysis. I just want to add
> something from Dr. Howard Johnson's book on this stuff. His claim is
> that you can treat a pcb trace as a lumped system if the trace is less
> than 1/4 * 'length of the edge
> Before you create another board, could you try using a razor to cut
> all the logic analyzer traces right near or at the vias?
I haven't made any boards yet - I'm trying to avoid making more than
one ;-)
I suppose I could make the board and just leave the via wires out,
which disconnects the s
Yesterday I was pointed by someone to a bug in one of my slotted symbols
at gedasymbols -- later I found two more related bugs.
It concerns
Comp-Quad-LM339_Type-1.sym
OpAmp-Dual-1.sym
OpAmp-Quad-1.sym
Bug should be fixed now, sorry if someone had trouble caused by these
symbols.
The error resul
Tim Hanson wrote:
> I've laid out an interface to a 133Mhz SDRAM, and the path lengths
> were similar to yours. Works great. No LA connector, though.
> Tim
>
I just looked at the reference design for atmel AT91SAM9260 and it uses
similar if not the same memory. Guess what, no clock terminati
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