At the very least, it seems that there should be a way to specify that any
pin with the same number satisfies the connection.
fairly ridiculous assumption especially with ICs, many of which
specifically say something like all GND/VCC pads must be connected.
The point of properly drawn symbols
On 02/03/2010 03:33 AM, timecop wrote:
At the very least, it seems that there should be a way to specify that any
pin with the same number satisfies the connection.
fairly ridiculous assumption especially with ICs, many of which
specifically say something like all GND/VCC pads must be
On Feb 3, 2010, at 12:33 AM, timecop wrote:
At the very least, it seems that there should be a way to specify that any
pin with the same number satisfies the connection.
fairly ridiculous assumption especially with ICs, many of which
specifically say something like all GND/VCC pads must
On Feb 3, 2010, at 7:53 AM, Vanessa Ezekowitz wrote:
On Wed, 03 Feb 2010 06:47:19 -0500
Ethan Swint eswint.r...@verizon.net wrote:
On 02/03/2010 03:33 AM, timecop wrote:
At the very least, it seems that there should be a way to specify that
any pin with the same number satisfies the
On Tue, 2010-02-02 at 21:22 -0800, Dave N6NZ wrote:
I'm reposting this because the discussion died and I'd like to give
the topic a bump -- I think it needs some collective thought by the
group.
It seems to me that we are missing a way to specify a connectivity
satisfaction rule for a
On Feb 3, 2010, at 9:59 AM, Peter Clifton wrote:
The danger comes if you don't populate the switch. This then causes
break in the board connectivity.
True enough. But population options are an orthogonal conceptual axis. Not
populating the microcontroller causes a loss of functionality,
I've just join the list recently and I've also encountered this problem.
In my view, the current gschem/PCB approach gives all the liberty to the
designer although obliges him to take all the decisions. (a bit like spider
man, with great power comes great responsibility :-)
I was using IRLD024
I ran into the same thing four times within the last week, just tinkering
with some old projects:
* A common four-pin SPST momentary button with two pairs of electrically
connected pins,
* A DB25 connector had its metal metal shield/shell connected to the two
primary mounting holes,
* A
I've got a pcb where close tracks through polygons are leaving thin shards of
copper between tracks. These are 8 mil tracks on a 10 mil grid. Seems to me
these have always been cleared out in the past because they are below minimum
copper size, but then again, I usually close space my tracks
I seem to have hit a regression in the quality of output from the
autorouter and/or trace optimiser in moving from pcb20081128 to
pcb20091103. With 20091103 I end up with many Manhattan traces that
the trace optimiser refuses to miter, see the attached images. If you
wish to reproduce this, the
Hey all,
I was trying to do a simple gnucap simulation of a full wave rectifier
circuit...probably something wrong in my schematic :(
Attached is my schematic test.sch, here's what i did:
cc...@studio:~/source/gaf/test$ gnetlist -g spice -o test.net test.sch
cc...@studio:~/source/gaf/test$
On Wednesday 03 February 2010, Chris Cole wrote:
gnucap tran 1s 10s
#Time
0.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Any suggestions?
You need to specify what to print first.
Before the tran
On Feb 3, 2010, at 7:51 PM, Dave N6NZ wrote:
I've got a pcb where close tracks through polygons are leaving thin shards of
copper between tracks. These are 8 mil tracks on a 10 mil grid. Seems to me
these have always been cleared out in the past because they are below minimum
copper
Hi,
First time using TSSOP48.
All rats, except those to/from TSSOP48, were successfully autorouted.
Is this a limitation in version 20080202 of pcb, or am I missing
something?
Stan
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Check your bloat/shrink settings, and keep-out style. It may not
allow traces as close together as the TSSOP's pads are.
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