On Sat, Sep 04, 2010 at 01:16:01AM -0400, Rick Collins wrote:
snip
But I suppose it is better to re-invent the wheel. There is no reason to
try to foster any sort of compatibility in file formats between all the
different CAD tools. There are always conversion programs to be written,
Am 04.09.2010 05:29, schrieb Rick Collins:
XML? What's wrong with XML? Heavy? How heavy are a few electrons anyway?
There is already a preliminary XML based CAD data spec proposed by IPC,
you know, the guys who write specs for the PCB assembly industry...
I don't know if it is the best
Am 04.09.2010 06:19, schrieb Ronald Mathias:
I transform the Verilog code containing behavioral statements into
verilog code that contains only gate level instantiations. This is
passed as input to ABC Logic synthesis tool. Finally the
output generated by ABC is passed to
On Fri, 2010-09-03 at 15:10 -0500, Kipton Moravec wrote:
I upgraded my Ubuntu 08.04 to 10.04 and now gschem will not work.
k...@red:/home/backup/Work/BuddiPole/Schematic/condisp $ gschem
condisp-*.sch
gschem: error while loading shared libraries: libltdl.so.3: cannot open
shared object
On Thu, 2010-09-02 at 16:11 -0400, Ethan Swint wrote:
I just can't figure out why can't the Crosshair snaps to pins/pads work
when
the component is locked. As far as I know, locking a component is for to
lock
the position of the component.
What a coincidence. We were just discussing
On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote:
As a kludge, call your layer by one of the magic names outline or
route and it will be ignored by the DRC, and treated as non-copper.
Regards,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of
On 9/3/10, Stefan Salewski m...@ssalewski.de wrote:
On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote:
Can I get pcb to either treat a layer other than the default silk as
non-metal
(so it would not short pads and mess up nets),
No, currently we have only one silk layer. You
Hello, DJ;
On 9/4/10, DJ Delorie d...@delorie.com wrote:
Our DRC engine could use a complete rewrite. It doesn't get arcs
right, for example.
Could you elaborate on the arcs, please? what it doesn't do?
Thanks,
Ineiev
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On Thu, 2010-09-02 at 12:42 -0400, DJ Delorie wrote:
Well, I did a git fetch/rebase, built, and installed... and still
there. About says 20100214, gitk says no commits since May, do I
have the wrong repository? The gschem binary is dated today.
What is the SHA1 of your repository head. (Not
gene glick wrote:
Stefan Salewski wrote:
On Sat, 2010-08-28 at 20:35 -0400, gene glick wrote:
I haven't yet put my finger on what operations cause this, but the
PCB GUI window keeps growing larger than my screen! Anybody know
what gives?
yep, sorry about that -
PCB version 20091103
OS :
On Sat, Sep 04, 2010 at 01:37:32AM -0400, DJ Delorie wrote:
If we tagged individual objects with rules it would be difficult to edit
rules in a systemetic way. So I don't think that's a good way to go.
No, we tag objects with rule *names*. Hopefully rules can nest, so
you can have
On Sat, Sep 04, 2010 at 01:16:01AM -0400, Rick Collins wrote:
Don't hold back, tell us how you really feel!
The spec is large because it addresses a wide range of design
aspects, which is one of the great reasons for using it, one file
for the entire design, schematic, layout, mechanical,
On Sat, Sep 04, 2010 at 01:38:15AM -0400, DJ Delorie wrote:
1. Refuse to export-as-footprints any PCB with more than one copper
layer. This will likely eliminate the most common problems.
Edge connectors.
Hmm. How about two copper layers, which would by default map to the
top and
I'll have to save a sample next time it happens, I can't reproduce it
manually :-P
Mostly it's when you're using the global puller or toporouter and it
makes all those sweeping graceful curves.
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What is the SHA1 of your repository head. (Not including any local
patches)?
I've tried to reproduce the bug, but so far haven't been able to.
And, of course, now I can't reproduce it either :-P
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On Sat, 2010-09-04 at 07:54 -0400, gene glick wrote:
gene glick wrote:
OK, maybe now I do understand your problem.
Your problem may be, that your GTK+ PCB main window grows horizontally,
because there is not enough space available to show all text, that is
the Menu text, filename, coordinates of
What's your screen resolution?
I can reproduce the window grows feature, but only if I start with a
really small window, and it only grows so far then stops.
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But suppose the user creates a rule like, all traces on Layer 3 must
be at least 5mm apart, and then saves the file and reloads it. Now the
information about what traces are affected is lost, except that all the
traces on Layer 3 are coincedentally tagged with the rule.
What if the user
How do you know PCB won't ever run on cell phones, or over a slow
network link, or on an embedded device or network PC or overtaxed
virtual machine?
iPcb . . .
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Hmm. How about two copper layers, which would by default map to the
top and bottom layers (whatever they are) on the PCB that the footprint
is being used in?
Stripline Antennas
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Andrew Poelstra wrote:
suppose the user creates a rule like, all traces on Layer 3 must
be at least 5mm apart, and then saves the file and reloads it. Now the
information about what traces are affected is lost, except that all the
traces on Layer 3 are coincedentally tagged with the rule.
What
Andrew Poelstra wrote:
How do you know we won't one day
need to work with 1000-layer boards when suddenly it /does/
matter how heavy the file format is?
As in 3D circuitry in printed organic semiconductor...
printed along with volume-defining material for circuit and package in one...
We'll
On Sep 4, 2010, at 4:30 AM, Ineiev wrote:
Hello, DJ;
On 9/4/10, DJ Delorie d...@delorie.com wrote:
Our DRC engine could use a complete rewrite. It doesn't get arcs
right, for example.
Could you elaborate on the arcs, please? what it doesn't do?
I've been running into trouble with the
On Sep 4, 2010, at 4:30 AM, Ineiev wrote:
Hello, DJ;
On 9/4/10, DJ Delorie d...@delorie.com wrote:
Our DRC engine could use a complete rewrite. It doesn't get arcs
right, for example.
Could you elaborate on the arcs, please? what it doesn't do?
I've been running into trouble with
On Sat, Sep 4, 2010 at 1:11 PM, Peter Clifton pc...@cam.ac.uk wrote:
As a kludge, call your layer by one of the magic names outline or
route and it will be ignored by the DRC, and treated as non-copper.
Peter, thanks for the tip.
I may be doing something wrong, but even following the tips at
On Sat, Sep 4, 2010 at 1:24 PM, Ineiev ine...@gmail.com wrote:
Probably this patch may be used as a workaround.
Put your non-copper layer into a distinct layer group
(File-Preferences-Layers, Groups Tab), add to the layer an attribute
named PCB::skip-drc (Edit-Edit attributes of-Current
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Am 04.09.2010 18:18, schrieb DJ Delorie:
How do you know PCB won't ever run on cell phones, or over a slow
network link, or on an embedded device or network PC or overtaxed
virtual machine?
iPcb . . .
On Sat, 4 Sep 2010 11:24:38 +
Ineiev ine...@gmail.com wrote:
Probably this patch may be used as a workaround.
Why don't we just push this patch to HEAD? This works just great.
Thanks,
Levente
--
Levente Kovacs
http://levente.logonex.eu
___
Ineiev, thanks for the patch, it applied fine. However, I'm unable to find the
(Edit-Edit attributes of-Current Layer). Is it placed somewhere else,
or can I manually edit the .pcb file for the same result?
I'm using pcb source tree from git, version 1.99z.
Do you have a local
At 11:49 AM 9/4/2010, you wrote:
On Sat, Sep 04, 2010 at 01:16:01AM -0400, Rick Collins wrote:
Don't hold back, tell us how you really feel!
The spec is large because it addresses a wide range of design
aspects, which is one of the great reasons for using it, one file
for the entire
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Hash: SHA1
Am 04.09.2010 01:44, schrieb Andrew Poelstra:
Hey all,
I am working on the structuring PCB files in terms of functional blocks,
and generalizing/extending the DRC rule format. (Things have slowed down
as summer is ending but I am still
I am currently having a conversation in the FreePCB forum about
DRC. I think copper only checking is not adequate. There are design
rules regarding solder mask which can not be checked properly just by
checking copper to copper rules.
Is there any checking done on the solder mask layer?
If
On Sat, Sep 04, 2010 at 06:37:37PM -0400, Rick Collins wrote:
So are you suggesting that we should, at this time, plan for running
PCB on a cell phone? Do you want to design PCB to work on overtaxed
virtual machines, if so, I expect there will be a lot more important
things to optimize than
How do you know PCB won't ever run on cell phones, or over a
slow network link
I have run gEDA and PCB over VNC, on slow links. Not fun.
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In parallel to how we want to implement the PCB file format, why don't
we have a separate thread on *what* we want to implement? I'll propose
the following as a starting point:
1) Better angle support: include rotation (in degrees,
rotation/translation matrix, whatever) as a location
Andrew Poelstra wrote:
The point is that we can't be sure what the future will bring in terms
of IOPS, storage capacity (even big servers often RAID together dozens
of small drives to get high speeds against low capacity).
This kind of argument goes against any change. geda development
Peter Clifton wrote:
On my various OpenGL branches, there is a patch which disables snapping
to pads on layers which you aren't on. (IE.. only snap to component side
pads if you are on a component copper layer).
I noticed this and liked it :-)
I don't think it can be separated too easily
Stefan Salewski wrote:
Please try this: Select File-Preferences, and then General, and
Alternate window layout to allow smaller horizontal size. And try Put
layout name on the window title bar below.
That is a good work around, thanks!
DJ:
What's your screen resolution?
1280 X 800. I have
On Sun, Sep 05, 2010 at 03:00:45AM +0200, kai-martin knaak wrote:
Andrew Poelstra wrote:
The point is that we can't be sure what the future will bring in terms
of IOPS, storage capacity (even big servers often RAID together dozens
of small drives to get high speeds against low capacity).
On Sat, Sep 04, 2010 at 07:50:51PM -0400, Ethan Swint wrote:
In parallel to how we want to implement the PCB file format, why
don't we have a separate thread on *what* we want to implement?
I'll propose the following as a starting point:
I have one more suggestion: the facility to create
On Sep 3, 2010, at 9:11 PM, Andrew Poelstra as...@sfu.ca wrote:
On Fri, Sep 03, 2010 at 11:29:58PM -0400, Rick Collins wrote:
XML? What's wrong with XML? Heavy? How heavy are a few electrons anyway?
For most data, XML ends up being 50% tags (and 50% data). It's hard to
read for
On Sep 3, 2010, at 9:45 PM, Andrew Poelstra as...@sfu.ca wrote:
On Fri, Sep 03, 2010 at 04:44:14PM -0700, Andrew Poelstra wrote:
However, this also brings the ability to edit PCB components individually,
which means that some parts could have different layers than others, for
On Sep 4, 2010, at 8:49 AM, Andrew Poelstra as...@sfu.ca wrote:
On Sat, Sep 04, 2010 at 01:16:01AM -0400, Rick Collins wrote:
Don't hold back, tell us how you really feel!
The spec is large because it addresses a wide range of design
aspects, which is one of the great reasons for
iPAd is about as closedsores and proprietary as it gets; you sure you
want to support that?
On 5 Sep 2010 11:57, Steven Michalske [1]smichal...@gmail.com
wrote:
On Sep 4, 2010, at 8:49 AM, Andrew Poelstra [2]as...@sfu.ca wrote:
On Sat, Sep 04, 2010 at
On Sep 4, 2010, at 6:00 PM, kai-martin knaak k...@familieknaak.de wrote:
Andrew Poelstra wrote:
The point is that we can't be sure what the future will bring in terms
of IOPS, storage capacity (even big servers often RAID together dozens
of small drives to get high speeds against low
Yes,
I like walled gardens, you only let in those you trust. Don't like the walled
garden don't use it.
Anyhow, the software is free. Who cares about MY platform of choice be it
Linux, Mac OS X, or windows, all of which geda supports, and more.
On Sep 4, 2010, at 8:05 PM, timecop
Hi,
Thanks a lot.
Regards
Ronald Mathias
On 9/4/10, Philipp Klaus Krause [1]...@spth.de wrote:
Am 04.09.2010 06:19, schrieb Ronald Mathias:
I transform the Verilog code containing behavioral statements
into
verilog code that contains
On 9/4/10, DJ Delorie d...@delorie.com wrote:
Ineiev, thanks for the patch, it applied fine. However, I'm unable to find
the
(Edit-Edit attributes of-Current Layer). Is it placed somewhere else,
or can I manually edit the .pcb file for the same result?
I'm using pcb source tree from git,
On Sep 4, 2010, at 4:50 PM, Ethan Swint wrote:
In parallel to how we want to implement the PCB file format, why don't we
have a separate thread on *what* we want to implement? I'll propose the
following as a starting point:
1) Better angle support: include rotation (in degrees,
Does anybody want to help me make a PSGroove hardware project for sony
ps3. Atommann's baby came early and I need someone else to help me
finish it.
[1]http://www.maxconsole.net/showthread.php?155644-Open-source-ps-jailb
reak-hardware-designp=1258686#post1258686
References
1.
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