Re: gEDA-user: Functional blocks and PCB format changes

2010-09-14 Thread Stephan Boettcher
I prefer: # -*- makefile -*- CSA-L%.sch: CSA-1.sch Makefile sed 's,^\(refdes\|netname\)=,L$*_,' $ $@ CSA-N%.sch: CSA-2.sch Makefile sed 's,^\(refdes\|netname\)=,N$*_,' $ $@ FSH-S%.sch: FSH-1.sch Makefile sed 's,^\(refdes\|netname\)=,S$*_,' $ $@

Re: gEDA-user: Functional blocks and PCB format changes

2010-09-14 Thread Stephan Boettcher
Steven Michalske smichal...@gmail.com writes: Now we may want to write a parser, and emitter, but that is a good amount of work, to serialize a data structure in the code that could be output be a data serializer that just works. The emitter shall conserve order and formatting (probably not)

gEDA-user: gschem : minor beautification

2010-09-14 Thread Camille Delbegue
Hello, This patch place the scrollbars and the drawing area in a table, this prevents that the scrollbars doesn't intersect in the bottom right corner. -- Kam diff --git a/gschem/include/prototype.h b/gschem/include/prototype.h index 5948c74..c0fc760 100644 --- a/gschem/include/prototype.h +++

Re: gEDA-user: Functional blocks and PCB format changes

2010-09-14 Thread Ethan Swint
On 09/13/2010 09:57 PM, Ouabache Designworks wrote: pin: pinNumber: 2 pinName: rst x1: 1234 y1: 4321 x2: 2345 y2: 4321 layer: component or pinpinNumber2/pinNumberpinNamerst\pinNamex11234\x1y

Re: gEDA-user: Functional blocks and PCB format changes

2010-09-14 Thread Phil Frost
On Mon, Sep 13, 2010 at 04:25:49PM -0700, Steven Michalske wrote: pin: pinNumber: 2 pinName: rst x1: 1234 y1: 4321 x2: 2345 y2: 4321 layer: component or pinpinNumber2/pinNumberpinNamerst\pinNamex11234\x1y14321\y1x22345\x2y25432\y2layercomponent\layer\pin I would point

Re: gEDA-user: Functional blocks and PCB format changes

2010-09-14 Thread Stephan Boettcher
Phil Frost ind...@bitglue.com writes: I would point out a valid YAML representation of the above is also: {pin: {pinNumber: 2, pinName: rst, x1: 1234, y1: 4321, x2: 2345, y2: 4321, layer: component}} Neither sed nor awk can process XML or YAML the right way in all cases without

Re: gEDA-user: next PCB release - 1.99za vs 4.0

2010-09-14 Thread Andrew Poelstra
On Mon, Sep 13, 2010 at 10:20:52PM -0400, Matthew Sager wrote: [*] We need a better term for drawing layers, since layer means something specific in PCB design. Or another name for physical layers. Or something ;-) How about overlay? Canvas comes to mind. It

Re: gEDA-user: Functional blocks and PCB format changes

2010-09-14 Thread gedau
On Mon, Sep 13, 2010 at 11:26:28AM -0400, Joshua Boyd wrote: On Fri, Sep 03, 2010 at 09:08:25PM -0700, Andrew Poelstra wrote: XML is far too heavy, agreed, and it's signal-to-noise ratio is abysmal. I think that using a Lisp (or Lispy-looking) format would be extensible, easy to parse, and

Re: gEDA-user: next PCB release - 1.99za vs 4.0

2010-09-14 Thread Windell H. Oskay
On Sep 14, 2010, at 7:23 AM, Andrew Poelstra wrote: On Mon, Sep 13, 2010 at 10:20:52PM -0400, Matthew Sager wrote: [*] We need a better term for drawing layers, since layer means something specific in PCB design. Or another name for physical layers. Or something ;-) How about

Re: gEDA-user: next PCB release - 1.99za vs 4.0

2010-09-14 Thread DJ Delorie
I like canvas - it's a more popular idiom than cel. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user

Re: gEDA-user: next PCB release - 1.99za vs 4.0

2010-09-14 Thread Windell H. Oskay
I like canvas - it's a more popular idiom than cel. Indeed it is. My concern about canvas is that it does not convey a relationship to our physical layers. In some cases it would be reasonable to expect a canvas to refer a full layer or even to a stack of layers. IMHO, it would be beneficial

Re: gEDA-user: next PCB release - 1.99za vs 4.0

2010-09-14 Thread Andrew Poelstra
On Tue, Sep 14, 2010 at 02:57:31PM -0400, Windell H. Oskay wrote: I like canvas - it's a more popular idiom than cel. Indeed it is. My concern about canvas is that it does not convey a relationship to our physical layers. In some cases it would be reasonable to expect a canvas to refer

Re: gEDA-user: (hierarchy-uref-mangle disabled) doesn't seem to work when generting a bom

2010-09-14 Thread Mike Crowe
Hi all I resolved this issue (given enough time even a monkey can solve his problems!). I'm posting just for future reference. I was using (hierarchy-uref-separator _) instead of (hierarchy-uref-separator /) The separator appears to be important even if it is disabled by

Re: gEDA-user: next PCB release - 1.99za vs 4.0

2010-09-14 Thread Frank Bergmann
On 12.09.2010 00:20, Peter Clifton wrote: (Can someone who uses / has used keepouts on another package describe for me how they work, or how you use them?) (In our company we are using a 5 year old package that has support for keepouts. It has pre-defined one keepout layer where the user can

Re: gEDA-user: (hierarchy-uref-mangle disabled) doesn't seem to work when generting a bom

2010-09-14 Thread kai-martin knaak
Mike Crowe wrote: I resolved this issue (given enough time even a monkey can solve his problems!). I'm posting just for future reference. Did you post a big report? The separator appears to be important even if it is disabled by (hierarchy-uref-mangle disabled) Ouch. Magic characters

Re: gEDA-user: next PCB release - 1.99za vs 4.0

2010-09-14 Thread John Griessen
On 09/13/2010 05:07 PM, John Doty wrote: On Sep 13, 2010, at 2:27 PM, DJ Delorie wrote: So let me rephrase: Why have seven geometric holes, one for each layer, when we can have one geometric hole applied to the whole composite? snip My notion is that you need a general mechanism to align

Re: gEDA-user: next PCB release - 1.99za vs 4.0

2010-09-14 Thread Andrew Poelstra
On Tue, Sep 14, 2010 at 10:34:23PM -0500, John Griessen wrote: On 09/13/2010 05:07 PM, John Doty wrote: On Sep 13, 2010, at 2:27 PM, DJ Delorie wrote: So let me rephrase: Why have seven geometric holes, one for each layer, when we can have one geometric hole applied to the whole