The most relevant of those can be found with a google search. Good luck!
--
Anthony Blake
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Hi all,
-Original Message-
From: geda-user-boun...@moria.seul.org
[mailto:geda-user-boun...@moria.seul.org] On Behalf Of Armin Faltl
Sent: Saturday, November 20, 2010 11:53 AM
To: gEDA user mailing list
Subject: Re: gEDA-user: a different approach to 3D modeling
Patrick Doyle
Hi all,
I've always hated the lower-case letter 's' in PCB, but couldn't come up
with a better one until now. And if anyone knows where I could put it to
make gsch2pcb use it, I'd be much obliged.
Cory
Symbol('s' 10)
(
SymbolLine(0 50 20 50 8)
SymbolLine(20 50 25 45 8)
Hello mailing list,
I need some help here. I want to use gschem to create a hierarchical
design and simulate that using icarus verilog. gnetlist -g verilog
works fine, but I have some trouble figuring out how to create a
matching symbol for the schematic and using gnetlist to
On Sun, 2010-11-21 at 02:03 -0800, Cory Cross wrote:
Symbol('s' 10)
(
SymbolLine(0 50 20 50 8)
SymbolLine(20 50 25 45 8)
SymbolLine(20 40 25 45 8)
SymbolLine(5 40 20 40 8)
SymbolLine(0 35 5 40 8)
SymbolLine(0 35 5 30 8)
On 11/19/10 12:21 PM, Peter Clifton wrote:
http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d_packages_mockup3.png
http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d_packages_mockup4.png
Perhaps pixel shaders and bump mapping is a little overkill for a few
resistors, but it has
On 11/21/2010 11:49 AM, Dave McGuire wrote:
Perhaps pixel shaders and bump mapping is a little overkill for a few
resistors, but it has kept me amused for a while.
Looks fab! Will actually be useful. Why not have processors churn for us?
Overkill? There are so many ways to kill the problem
On 21 November 2010 02:05, Peter Clifton pc...@cam.ac.uk wrote:
On Sat, 2010-11-20 at 22:48 +, Gareth Edwards wrote:
The usability of the Blender 2.5x betas is a step-change from the
existing versions. I'm not saying it's easy, but it's considerably
less insane.
Just installed it, seems
John Griessen wrote:
How could one have overkill?
Inefficient use of developer cycles. Traditionally, the most valuable
resource open source projects.
---)kaimartin(---
--
Kai-Martin Knaak
Öffentlicher PGP-Schlüssel:
http://pgp.mit.edu:11371/pks/lookup?op=getsearch=0x6C0B9F53
Is it possible to create a symbol with two types of slots. For
example, in a 4 OR gates logic chip, one slot type would be the OR
gate, while the other slot type would be the power connections. I see
people typical wire the pins that are not part of a slot to nets, but
that seems
On Sun, 2010-11-21 at 16:52 -0800, Oliver King-Smith wrote:
Is it possible to create a symbol with two types of slots. For
example, in a 4 OR gates logic chip, one slot type would be the OR
gate, while the other slot type would be the power connections. I see
people typical wire the
On Sun, 2010-11-21 at 22:45 +0100, kai-martin knaak wrote:
John Griessen wrote:
How could one have overkill?
Inefficient use of developer cycles. Traditionally, the most valuable
resource open source projects.
Developers having fun are happy developers, and might even find time for
some
On Nov 21, 2010, at 7:30 PM, Peter Clifton wrote:
That is a slightly bad
example though, as all the 74* symbols in the library also have hidden
net= attributes which wire up their power pins. The idea is solid
though.
Every tutorial on gEDA should state up front:
LIBRARY SYMBOLS ARE ONLY
If it was me, I think I'd make a script for some 3D modelling package like
FreeCAD to generate a 3D model using PCB's XY place file output.
The process would be:
1. make FreeCAD 3D models for each of the components
2. generate an XY place file, board outline file and drill file in PCB
3.
Hi Chris,
Last time I checked, when netlisting a schematic, the
gEDA Verilog netlister does not order the top MODULE portnames
by user specified sequence order(such as using the refdes
attribute's numeric suffix value of I/O PADS to order the
portnames).
Since most Verilog simulators (including
On Sunday 21 November 2010, Paul Tan wrote:
Since most Verilog simulators (including Icarus Verilog)
support EXPLICIT connection method for the lower level
Module Instanciations, so it is not absolutely necessary
(although desirable) to match the Module portname order
with the Module
Peter,
Different symbols for each slot is no problem. I will try that
tomorrow.
I was messing around with the slot=1 slot=2 trying to make things work
and getting no where. Does the slot keyword do anything other than
define the beginning of a slot?
Oliver
in the process of cnc-milling a pcb with a custom shape using pcb2gcode
[1], i created a polygon on a separate layer...
Have you ever tried the g-code exporter included in PCB?
I've never been able to make pcb2gcode work with minimally complex boards.
Hello Al Davis and Paul Tan,
you solved problem, thank alot. To summarize:
If I create schematic and assign the attribute 'netname=name' to the
nets coming from our going to the i-/opads and a symbol with the
attribute 'pinnumber=name' at the appropriate pin, they are connected
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