Re: gEDA-user: going multi core

2011-01-26 Thread Peter TB Brett
- Original message - > just one such core. Can I expect a spectacular speed-up of gschem > and pcb? Or are they throttled by the graphic card anyway? gschem is a single-threaded application. It runs on one core, no matter how many you have. So no, don't expect a big speed up.

Re: gEDA-user: Alternate Platforms

2011-01-26 Thread Dave McGuire
On 1/26/11 11:59 PM, rickman wrote: BTW, is Android multitasking or is it single tasking like the iPad OS? Android is layered atop Linux. The iPad OS (also the iPhone OS, called iOS) is multitasking as of release 4.0. Incidentally, it too is a UNIX-based platform...only its user interfa

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread rickman
On 1/26/2011 3:50 PM, Peter Clifton wrote: On Wed, 2011-01-26 at 13:33 -0500, rickman wrote: I guess I am missing something significant with this. Why wouldn't the inductor just be a component on the schematic and a component in layout just like any other inductor? The only difference is that

gEDA-user: Alternate Platforms

2011-01-26 Thread rickman
Tablet PCs are going to be taking off big time over the next year or two. This is the ideal platform that I have wanted for a long time. But for now at least, they don't run Windows or even Linux. They run the Android OS on ARM processors. I don't really know how closely the UI maps to a st

Re: gEDA-user: going multi core

2011-01-26 Thread George M. Gallant, Jr.
If the new system is anything like this list, you should expect a significant slowdown as the CPUs argue amongst themselves as to who gets to do what, when and how not to do something. I have not seen a significant advantage to single process geda tools execution. I suspect that some of the backe

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread Stephen Ecob
> Similar to the last is a jumper location that is connected by copper by > default to be cut if an open is needed.  Consider this to be a 1 bit PROM. > > Rick Yes, they're useful. I use them a lot on early revision boards when the design is still subject to change in some areas. __

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread rickman
On 1/26/2011 7:00 PM, Stephen Ecob wrote: A similar "track is component" scenario: PCB fuse track - a dirty trick I've seen in some Honywell boiler controllers.. where a deliberately thin trace is used to act as a fuse. That certainly is a dirty trick! (But on a very tight budget it could make

gEDA-user: going multi core

2011-01-26 Thread Kai-Martin Knaak
There is going to be a new desktop on my desktop at work! It is going to be the the usual upgrade in computational power: More memory, more storage, more speed. Speed is supposed to be delivered by four cores (AMD athlon). My current desktop contains just one such core. Can I expect a spectacular

Re: gEDA-user: pcb: possible to have multiple silk layers?

2011-01-26 Thread Colin D Bennett
On Wed, 26 Jan 2011 21:38:39 +0100 Kai-Martin Knaak wrote: > Colin D Bennett wrote: > > > For the same purpose I also wish we could group objects together > > so that my imported > > text/graphics I add to the board (output from pstoedit, which are >

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread Stephen Ecob
> A similar "track is component" scenario: > > PCB fuse track - a dirty trick I've seen in some Honywell boiler > controllers.. where a deliberately thin trace is used to act as a fuse. That certainly is a dirty trick! (But on a very tight budget it could make sense). So there are several use cas

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread Peter Clifton
On Thu, 2011-01-27 at 08:32 +1100, Stephen Ecob wrote: > > Perhaps I was going a bit far to suggest full DRC for the actual antenna > > design. What I really meant was not loosing information for net > > connectivity checking leading up the antenna. > > Thinking longer term, why not support DRC ch

Re: gEDA-user: Visual cue of zero length pin endpoint

2011-01-26 Thread Peter Clifton
On Wed, 2011-01-26 at 22:23 +0100, Kai-Martin Knaak wrote: > >> While at it: The marker should _not_ scale with zoom. Make this behaviour > >> default, but optional. So the old behavior can be restored. > > > NAK (I think) - so printing works, > > Is printing to postscript hard wired to scree

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread Stephen Ecob
> Perhaps I was going a bit far to suggest full DRC for the actual antenna > design. What I really meant was not loosing information for net > connectivity checking leading up the antenna. Thinking longer term, why not support DRC checking of inductance and resistance for specially tagged traces ?

Re: gEDA-user: Visual cue of zero length pin endpoint

2011-01-26 Thread Kai-Martin Knaak
Peter Clifton wrote: >> This eye-catching marker should not print (in postscript). > > The net-end red dot is effectively a DRC overlay warning you have left > something unconnected. I would be inclined to make sure it does print, > otherwise PDF schematics sent to collaborators for review would

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread Peter Clifton
On Wed, 2011-01-26 at 13:33 -0500, rickman wrote: > I guess I am missing something significant with this. Why wouldn't the > inductor just be a component on the schematic and a component in layout > just like any other inductor? The only difference is that the footprint > defined for the comp

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread Peter Clifton
On Wed, 2011-01-26 at 18:34 +0100, Stephan Boettcher wrote: > > The inductor will end up as a shaped piece of copper tracking, and at > > this point, you realise that "net" is a very DC term! > > The inductor could be a subschematic with shorted pins via two short > symbols, with a net in between

Re: gEDA-user: pcb: possible to have multiple silk layers?

2011-01-26 Thread Kai-Martin Knaak
Colin D Bennett wrote: > For the same purpose I also wish we could group objects together > so that my imported > text/graphics I add to the board (output from pstoedit, which are > composed of many separate polygons) can be easily moved, rotated, or >

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread Phil Taylor
> you must also connect the two pins in the schematic, or DRC will > complain about a short circuit. Ive had good luck giving multiple coppper pins and pads the same number in the footprint file. This only works for pins/pads that overlap. If not PCB will only enforce a connection to one

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread DJ Delorie
> I would think the pads of a footprint would not be checked against > one another with the same rules as traces. Is that what you are > saying? No, I'm saying some pads in a footprint can be marked to be ignored just for connectivity checking. You still want to do the rest of the DRC checks to

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread rickman
On 1/26/2011 1:55 PM, DJ Delorie wrote: Sure, you can use pads to make arbitrary traces in your element. But, you must also connect the two pins in the schematic, or DRC will complain about a short circuit. Once the nets are shorted in the netlist, it's not always easy to figure out which conne

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread DJ Delorie
Sure, you can use pads to make arbitrary traces in your element. But, you must also connect the two pins in the schematic, or DRC will complain about a short circuit. Once the nets are shorted in the netlist, it's not always easy to figure out which connections go to which side of your antenna.

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread rickman
On 1/26/2011 1:42 PM, DJ Delorie wrote: the footprint defined for the component would be the copper DRC sees that as a short circuit, not an element DRC will complain if pads are touching? Can you create arbitrary shaped pads? But they can't touch each other Do you have a way of creat

Re: gEDA-user: pcb: possible to have multiple silk layers?

2011-01-26 Thread rickman
On 1/26/2011 1:23 PM, Colin D Bennett wrote: Is there any way to set up multiple silk screen layers in pcb? The idea is that I want to be able to turn off display of the extra text/graphics on the silk layer that I have added to the board, but still be able to see the component outlines. For th

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread DJ Delorie
> the footprint defined for the component would be the copper DRC sees that as a short circuit, not an element. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread rickman
On 1/26/2011 12:34 PM, Stephan Boettcher wrote: Peter Clifton writes: On Mon, 2011-01-24 at 07:48 -0800, Ouabache Designworks wrote: The special symbols is supposed to fuse netnames as issued on the netlist, not labels on the schematic. ---

Re: gEDA-user: pcb: possible to have multiple silk layers?

2011-01-26 Thread DJ Delorie
Sorry, pcb doesn't support those things. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user

gEDA-user: pcb: possible to have multiple silk layers?

2011-01-26 Thread Colin D Bennett
Is there any way to set up multiple silk screen layers in pcb? The idea is that I want to be able to turn off display of the extra text/graphics on the silk layer that I have added to the board, but still be able to see the component outlines. For the same purpose I also wish we could group objec

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread Stephan Boettcher
Peter Clifton writes: > On Mon, 2011-01-24 at 07:48 -0800, Ouabache Designworks wrote: >> The special symbols is supposed to fuse netnames as issued on the >>netlist, >>not labels on the schematic. >>--- >>If you are also fusing the copper

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread DJ Delorie
I was thinking it would be easy to add a "notcopper" or "ignore_me" flag to element pads, but it wouldn't be as easy to make everything else work nicely with it. Tedious, mostly. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/

Re: gEDA-user: gschem: directly connecting two nets?

2011-01-26 Thread Peter Clifton
On Mon, 2011-01-24 at 07:48 -0800, Ouabache Designworks wrote: > The special symbols is supposed to fuse netnames as issued on the >netlist, >not labels on the schematic. >--- >If you are also fusing the copper on the board then I would kind o

Re: gEDA-user: Visual cue of zero length pin endpoint

2011-01-26 Thread Peter Clifton
On Mon, 2011-01-24 at 17:16 +0100, Kai-Martin Knaak wrote: > My proposal: > Make all endpoints point-like. There is no point in having a direction > of an endpoint. (pun intended) Put a blob with configurable size and > color at the end of every pin. Make it stand out by default. This is a > cue

Re: gEDA-user: Windows gEDA port

2011-01-26 Thread Bob Paddock
On Wed, Jan 26, 2011 at 1:21 AM, Terrance Hutchinson wrote: >   What about MinGW-w64 support? It also has the MinGW-w32 compiler as >   well. >   I find that the MinGW-w64/w32 is a much better cross-compiler. Are you familiar with the TDM project? http://tdm-gcc.tdragon.net/ It bundles w64 and