Hi,
I just installed gerbv 2.1.0 to check a design of mine. Looking at the
XY-files as drawn by gerbv, I notice that all the rotations are off by
excactly 180 degree.
Is this a bug in gerbv or in PCB? (tested with latest CVS version)
regards,
David
--
GnuPG public key:
Stefan == Stefan Salewski [EMAIL PROTECTED] writes:
I have 0.5 mm grid size, 0.25 mm line width and 0.25 mm Minimum
copper spacing in Preferences/Design Rule Checking.
It was clear for me that this can cause problems -- indeed it does.
Sometimes it is not possible to draw copper lines on
Steven == Steven Michalske [EMAIL PROTECTED] writes:
i put mine into source control, so that i can go back in time and work
on old files easily enough
when schematics reference a symbol you used years ago and you have
updated it, you may need the older one for the schematic. you
John == John Luciani [EMAIL PROTECTED] writes:
The 2005 version gives the correct centroid or may just default to
the value of the mark which happens to be the correct centroid for
this footprint.
Centroid coordinates are computed by averaging the coordinates of all
pads of an element
Ben == Ben Jackson [EMAIL PROTECTED] writes:
On Sun, Sep 28, 2008 at 12:49:45PM +0200, David Kuehling wrote:
Unfortunately, flooding 0603 components results in a thin copper
hair in between the pads, that is less than 6 mil and thus violates
design rules.
http://mosquito.dyndns.tv/~spock
tj == tj [EMAIL PROTECTED] writes:
I asked a question earlier about oval pads and I have located what I
am looking for as an example on the
http://www.gedasymbols.org/footprints/newlib/tests/14DIP_oval_pad.fp
page. However once I download it, how do I add it to a library? Like,
I want to
Hi,
I recently applied ground flooding to the component side of a PCB
design. Unfortunately, flooding 0603 components results in a thin
copper hair in between the pads, that is less than 6 mil and thus
violates design rules. Here is a screenshot that illustrates the
problem:
Hi,
doing ground-flooding I recently realized that all elements generated
via M4 macros COMMON_SMT_DIL_MIL / COMMON_SMT_DIL_MIL_MM have only half
the required pad clearance (5 mil instead of 10 mil). This is a bug in
pcb/m4/smt.inc, line 631, which declares PADCLEAR as 1000 (10 mil).
This is too
Ben == Ben Jackson [EMAIL PROTECTED] writes:
Look at: http://www.gedasymbols.org/scripts/search.cgi?key=0603
Are the CAPC*, and RES* footprints way too small?
CAPC0603 is *not* a 0603. The CAPC* and RES* footprints use metric
units, the CAPC0603 corresponds to a 0201 mil footprint. For the
DJ == DJ Delorie [EMAIL PROTECTED] writes:
The only way to manage paste is to write a script to adjust the pads,
copying from your official board to a separate paste board. You can
shrink/dice/remote pads as needed, then print the paste gerber from
the new file.
Hmm, according to
Peter == Peter TB Brett [EMAIL PROTECTED] writes:
On Friday 12 September 2008 15:52:19 David Kuehling wrote:
If I load such a netlist into PCB, it doesn't complain. But on
saving and re-opening my layout, it reports a syntax error for a
line:
Net(\_RESET\_ (unknown))
Well, that's *very
Peter == Peter Clifton [EMAIL PROTECTED] writes:
On Wed, 2008-09-10 at 11:02 +0200, David Kuehling wrote:
Note that the paren ')' terminating the element does not come on its
own line.
Was this an M4 footprint from the stock library? If so, which? (It
would make for much lazier
Hi,
I'm currently in the process of updating a design created quite some
time ago. If I take the original design, the DRC now finds errors,
where it didn't find any in the old version.
I think I created the design with pcb-20060822. Now I'm using
20070208p1 that comes with Ubuntu 7.10.
Errors
Peter == Peter Clifton [EMAIL PROTECTED] writes:
On Tue, 2008-09-09 at 20:54 +0200, David Kuehling wrote:
BTW I'm running gsch2pcb 1.6, included with Ubuntu 7.10's geda-utils
package version 1.0.1.20070626.
Its a little old, but I can't remember any particular bug-fixes to
gsch2pcb since
Hi,
after some debugging I found the error: One of my m4 fooprints ended on
the following line:
ElementLine [-7186 7283 7186 7283 800])
Note that the paren ')' terminating the element does not come on its own
line.
Now the parser in 'add_elements' overlooks the trailing paren, since the
Peter == Peter Clifton [EMAIL PROTECTED] writes:
On Mon, 2008-09-08 at 17:53 +0200, David Kuehling wrote:
I can't find the reason for that error. Is there any way I can make
gsch2pcb give some more output about _why_ it chose to delete an
element? Is anything known about that anomaly
Hi,
reading through the m4-style footprint definitions, I stumbled into the
metric vs. non-metric footprint definitions
(/usr/share/pcb/m4/geda.inc), i.e. 'RESC1005L', 'RESC1005N', 'CAPC1005L'
etc which are approximately the same as '0402'.
Now I'm just wondering, for parts that the manufacturer
Hi,
thanks for the quick answer,
Dan == Dan McMahill [EMAIL PROTECTED] writes:
reading through the m4-style footprint definitions, I stumbled into
the metric vs. non-metric footprint definitions
(/usr/share/pcb/m4/geda.inc), i.e. 'RESC1005L', 'RESC1005N',
'CAPC1005L' etc which are
Hi,
this is a problem that has bugged me for quite some time now: whenever I
use gsch2pcb to update my design, it deletes almost all elements, even
though nothing changed about them. gsch2pcb --fix-elements has the same
problem:
cp board.pcb board_new.pcb
gsch2pcb --fix-elements -v -v -v
Dan == Dan McMahill [EMAIL PROTECTED] writes:
David Kuehling wrote:
Hi,
I'm just wondering, how do I get sensible rotation information in the
centroid data for footprints that don't have a pin numbered '1', but
only a pin numbered '1B'. In my case that's a BGA footprint, where I
chose
Hi,
I'm just wondering, how do I get sensible rotation information in the
centroid data for footprints that don't have a pin numbered '1', but
only a pin numbered '1B'. In my case that's a BGA footprint, where I
chose pin numbers 1B..7E in accordance to the part's data sheet.
Do I have to
Stephen == Stephen Williams [EMAIL PROTECTED] writes:
We need to find a way to smooth this process. I suspect that there are
a lot of users willing to pay a few hundred dollars to get a
particular feature fixed/implemented, but the overhead of negotiating
a typical consulting contract would
Dan == Dan McMahill [EMAIL PROTECTED] writes:
David Kuehling wrote:
Hi, just another strange DRC error. This is caused by the
oldlib-generated footprint SMT_DIODE 15 8: Rules are minspace 5.92,
minoverlap 5.91 minwidth 5.91, minsilk 7.09 min drill 1.00, min
annular ring 15.75 Element Z50
Dan == Dan McMahill [EMAIL PROTECTED] writes:
David Kuehling wrote:
DJ == DJ Delorie [EMAIL PROTECTED] writes:
http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png
Could you post (or send me privately) the .pcb file?
Here is a simplified file that only contains the problematic
Hi,
the DRC tells me Line with insufficient clearance inside polygon. If
I do Ctrl+R on the line in question, the clearance is correctly shown as
5.91mils (actually 0.15mm). 0.15mm is also my configured DRC clearance.
Might that just be a rounding error which I can ignore?
regards,
David
--
DJ == DJ Delorie [EMAIL PROTECTED] writes:
the DRC tells me Line with insufficient clearance inside polygon.
If I do Ctrl+R on the line in question, the clearance is correctly
shown as 5.91mils (actually 0.15mm). 0.15mm is also my configured
DRC clearance.
Look for tiny traces under the
DJ == DJ Delorie [EMAIL PROTECTED] writes:
http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png
Could you post (or send me privately) the .pcb file?
Here is a simplified file that only contains the problematic footprint.
Quite possibly this is just a problem with the footprint? After
Hi,
just another strange DRC error.
This is caused by the oldlib-generated footprint SMT_DIODE 15 8:
Rules are minspace 5.92, minoverlap 5.91 minwidth 5.91, minsilk 7.09
min drill 1.00, min annular ring 15.75
Element Z50 has 5 silk lines which are too thin
near location
KURT == KURT PETERS [EMAIL PROTECTED] writes:
David, this is way off topic. But I noticed that your traces seem to
change sizes at the silk-screen for the Brown ones (Vcc Comp). Is
there any particular reason that you do that? Regards, Kurt
I followed some guidlines from the book Surface
Darrell == Darrell Harmon [EMAIL PROTECTED] writes:
David Kuehling wrote:
[..]
Or is it just a bad idea to connect die-attach-pads directly with
vias?
David
I assume this is an exposed pad type part. Most of these use the
exposed pad either for a good RF ground or heatsink or both
DJ == DJ Delorie [EMAIL PROTECTED] writes:
What Darrell said with emphasis on matrix of vias. I wouldn't use
just a single via on that part.
The other question, though, is should PCB *allow* you to put thermals
in pads? At the moment, it's not physically possible.
If that's impossible,
Ostheller, == Ostheller, Joel A [EMAIL PROTECTED] writes:
I am no expert (yet) and I am sure there may be many causes to your
issue - but I have noticed if the footprint attribute accidentally
gets deleted then it will remove your elements from your .pcb
Footprint attribute seems to be
John == John Luciani [EMAIL PROTECTED] writes:
On 09 Jan 2007 18:13:35 +0100, David Kuehling [EMAIL PROTECTED] wrote:
Hi,
I used both (analog) GND and PGND symbols in my layout. Now after
running gschem2pcb and loading the netlist file I see that those
symbols create two separated nets
Hi,
running gsch2pcb a second time to update the schematic makes it remove
almost all the elements, although the schematic didn't change much
(actually just some netlist changes):
gch2pcb -v -v project
[..]
Running command:
gnetlist -g gsch2pcb -o board.new.pcb -m
John == John Luciani [EMAIL PROTECTED] writes:
I make antennas by creating a footprint with multiple overlapping
pads. Each pad has the same pin number. For the schematic just create
a symbol with two pins that have the same pin number.
Thanks, I'll try that. Thinking about it, a standard
Hi,
reading through the manufacturer's design rules, I cannot find any
comments on how much distance silk text should keep from vias. Just
wondering, whether there problems one should be aware of (like silk
detaching and geting to places it doesn't belong?) Or can vias just be
overprinted?
John == John Luciani [EMAIL PROTECTED] writes:
I make antennas by creating a footprint with multiple overlapping
pads. Each pad has the same pin number. For the schematic just create
a symbol with two pins that have the same pin number.
Hi, thanks for that tip.
May I ask what kind of
Hi,
I used both (analog) GND and PGND symbols in my layout. Now after
running gschem2pcb and loading the netlist file I see that those symbols
create two separated nets.
Still I want to connect GND and PGND somewhere in my layout without
making the DRC complain. I tried to add a connection
DJ == DJ Delorie [EMAIL PROTECTED] writes:
Is there a way to change the default line thickness used by the
default font without increasing the font size itself?
Set the minimum silk width in the board sizes dialog. It will emit
gerbers with the right size, even if it shows up thinner on
Kai-Martin == Kai-Martin Knaak [EMAIL PROTECTED] writes:
On Sun, 31 Dec 2006 00:37:33 +0100, David Kuehling wrote:
I even experienced some segfaults when I tried to move elements.
Now after fixing the footprint everything seems to work quite right.
Still, pcb should not segfault even
Hi,
looking at my PC board I notice that the line thickness of element names
seems to be much smaller than the line thickness used for drawing
element outlines (which is 8 mil for my own footprints).
The PCB manufacturer I chose has the minimum allowed silk line thickness
specified as 0.18mm
Hi,
if I draw lines on the silk layer, those lines end up being green.
After triple-clicking those green lines, their color magically changes
to black. But when I draw arcs instead, the color is black from the
beginning.
Here is a screenshot illustrating the situation:
Hi,
I'm just playing around with my first PCB-file generated via gschem2pcb.
But even after about an hour of trying, I do not manage to reliably move
element-names around. Those elements were generated via gschem2pcb from
oldlib components.
I sometimes can move element-names using
I sometimes can move element-names using mouse-button-1 or button-2.
But not in all cases will pcb select the name for moving. Sometimes
it will move the element and sometimes it won't move anything. For
some elements (especially where the name is large compared to the
element outline) I
Karel == Karel Kulhavy [EMAIL PROTECTED] writes:
On Thu, Dec 14, 2006 at 09:17:33AM +0100, David Kuehling wrote:
For PCB that might be the same: if you distribute gerber files, you
distribute the *output* of PCB, which obviously doesn't contain
literal code from the footprints. If you
Stephen == Stephen Williams [EMAIL PROTECTED] writes:
I believe deceiving for a material profit is a criminal act, but
deceiving for a public benefit is not illegal.
Well, where I live (USA) theft is theft, no matter what the motive.
If I rob a bank and give all the money to a church or a
Hi,
Looking at the PCB docs it seems like SMD pads must either be round or
rectangular, never both? I'm just looking at the recommended land
pattern in this data sheet (PDF, page before last page):
http://www.ti.com/lit/gpn/bq24070
They'r drawing longish pads which are round on one end and
DJ == DJ Delorie [EMAIL PROTECTED] writes:
They'r drawing longish pads which are round on one end and
rectangular at the other end.
Also the die-attach pad has a very unusual complex polygonal form.
Both can be made from multiple pads. See (also attached):
Andy == Andy Peters [EMAIL PROTECTED] writes:
To continue on the GPL and BSD topic ... Just to clarify: if I use
GPLed or BSD-licensed tools to develop hardware, as well as using
GPLed symbols/footprints, am I obligated to open-source the hardware
design (the schematic, the PCB layout)?
Peter == Peter TB Brett [EMAIL PROTECTED] writes:
Hi folks, Slightly off-topic, but I need some suggestions: I'm
currently building an ADC board to go with an existing microprocessor
board I have available. It's going to have eight 100 kHz 12-bit serial
ADCs.
Now, the problem I have is
Hi,
thanks for your answer.
Ales Hvezda [EMAIL PROTECTED] writes:
[snip]
Found duplicate net name, renaming [+3.3V] to [BS1] WARNING: Trying
to rename something twice: +3.3V and +3.3V are both a src and dest
name This warning is okay if you have multiple levels of hierarchy!
This
Hi,
David Griffith [EMAIL PROTECTED] writes:
This is my first complex design and I have three annoying problems:
[..]
good coincidence and a good chance to add my problems to the list :) I'm
currently also just in the process of netlisting a complex design in
preparation for PCB layouting. I
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