Stephen Williams wrote:
I think there is a bug report related to this in the icarus verilog
bugs tracker already. automatic tasks are not supported yes, and
there is a patch that I recently applied that reports this as a
proper error.
Are there any plans to add automatic tasks or is that too
Stephen Williams wrote:
Günter Dannoritzer wrote:
...
How can I check that it works correct?
It is just as likely that you found a bug that is segfaulting instead
of tripping an assert. That is rare in Icarus Verilog because we're
so liberal with assertions, but it does happen from time
Jared Casper wrote:
On Sat, Aug 16, 2008 at 12:55 PM, Günter Dannoritzer [EMAIL PROTECTED]
wrote:
So with the latest development snapshot it gave me an assertion, but
with the git version a segmentation fault.
I saw this behavior as well, so I don't think it is your setup. Something
Hi,
I tried to install Icarus Verilog from git and wonder whether I did
something wrong, as when things go wrong it crashes with a segmentation
fault.
I have to say that I have the latest development snapshot installed in
parallel in the standard path.
So what I did with the git version is
Hi,
I tried compiling some Verilog code with a 'task automatic' statement
using Icarus Verilog 0.9.devel s20080429 and got the following assertion:
iverilog -o auto2.vvp auto.v
auto.v:16: syntax error
auto.v:3: assert: pform.cc:359: failed assertion lexical_scope ==
pform_cur_module
sh: line
Dan McMahill wrote:
[...]
\begin{shamelessplug}
If you're doing LateX documents and like Makefile's you might take a
look at latex-mk (http://latex-mk.sf.net). It is a set of makefile
fragments along with a couple of wrapper scripts. It manages
dependencies and all the building
Stephen Williams wrote:
[...]
Has anybody here used ghdl? freehdl? Relative merits? Which is
most active? The most portable? Easiest to use?
It just seems like ghdl has the most activity associated with it,
but FreeHDL doesn't look completely dead either. So what to choose?
For openSUSE you
al davis wrote:
On Friday 25 April 2008, Stephen Williams wrote:
As you know, this year's Icarus Verilog GSoC candidate is
working on a VHDL code generator back-end for Icarus Verilog.
Hooray! But suddenly the obvious question comes up, How are
we going to run these generated files? I'm here
Mike Jarabek wrote:
Hi,
You could try using a relative path, that is:
Replace Romfile.txt with ../sim/Romfile.txt
This might get you past the problem, at the expense of forcing the directory
structure to always have the file in the 'sim' directory. I think the Xilinx
tools can deal
Stephen Williams wrote:
Günter Dannoritzer wrote:
Hi,
I am using the system task $readmemh to init some ROM. Now my question
is, can I specify for the simulation with Icarus somewhere the path to
the file I am using with $readmemh?
I can think of 2 ways:
You can use $value$plusargs
Hi,
I am using the system task $readmemh to init some ROM. Now my question
is, can I specify for the simulation with Icarus somewhere the path to
the file I am using with $readmemh?
Here is my dilemma. My folder structure is as follows:
+ rtl/
+ tb/
+ sim/
+ syn/
In rtl/ and tb/ I have my
Matt Ettus wrote:
[...]
Günter,
I am also interested in trying Teal/Truss. Do you like using it? Is
it worth the effort to learn? And how well does it work with Icarus
in general?
Hi Matt,
Unfortunately I have not used it very much yet. I got the book about a
year ago and started
Stephen Williams wrote:
Question:
Does *anybody* use or even see value in the 32bit runtime support
that Icarus Verilog includes in 64bit builds? In particular, there
is support in the Icarus Verilog source for building simultaneously
a vvp (64bit) and a vvp32 (32bit) to support 32bit VPI's
Stephen Williams wrote:
Günter Dannoritzer wrote:
Hi,
I am looking into using Icarus Verilog with Teal/Truss, a C++ based
verification framework.
With Icarus 0.8.6 all tests but the last, with release of a_wire, are
working.
It's probably a matter of it not being implemented yet. Looks
Hi,
I am looking into using Icarus Verilog with Teal/Truss, a C++ based
verification framework.
http://trusster.com/
Actually, to be more precise, Truss is the verification framework
written in C++ and Teal are some utility classes, allowing to connect
Truss to Verilog simulators via the PLI
Werner Hoch wrote:
...
Unfortunatly I wasn't able to build it for openSUSE 10.3 on x86_64 arch.
The bz2_32bit_devel files are no longer part of openSUSE 10.3.
...
I ran into the same problem with the development snapshot. I assumed it
was just my limited knowledge about the changed packages
Stephen Williams wrote:
int is PLI_INT32 in your case. The static part is something
else altogether and perhaps more germain to your problem. You
don't say what's crashing, Stu's example or mine, etc., so we
have very little to go on.
Sorry for being so vague. I was more curious about the
Jason Elder wrote:
[...]
Finally I settled on OpenSUSE 10.2 with the GNOME desktop. SUSE has older
versions of both firefox and openoffice, but needed to make a choice so I
settled on this one. I really like it, especially the GNOME desktop with the
X-sumthin-or-other that adds desktop
Evan Lavelle wrote:
Günter Dannoritzer wrote:
[...]
Here are some information about that and a link to a previous discussion:
http://iverilog.wikia.com/wiki/Graffiti#SDF_support
I added a section to your entry covering the reasons for doing timing
simulations (same URL).
Haven't quite
Andy Peters wrote:
Does iverilog support SDF backannotation? The SDF has the delay
information.
Here are some information about that and a link to a previous discussion:
http://iverilog.wikia.com/wiki/Graffiti#SDF_support
Cheers,
Guenter
___
Stephen Williams wrote:
I've started a section in the Graffiti page of the Icarus Verilog
documentation wiki: http://iverilog.wikia.com/wiki/Graffiti
and I've sent the initial contents directly to Dan. If any other
Icarus Verilog ideas pop up, I can vet them and pass them on.
(Hmm... I
Hi,
I compiled the recent snapshot on my openSuse 10.2 x86_64 system and
recognized that by default, when running ./configure, it does not
compile with vvp32 support.
When I analyzed the verilog.spec file from the latest snapshot rpm, then
it calls ./configure with the --enable-vvp32 flag.
My
Stephen Williams wrote:
Günter Dannoritzer wrote:
[...]
This is for users who have a 32bit .vpi module from a 3'rd party. They
cannot use it with the 64bit vvp, but vvp32 will be able to load it
just fine. That's the *only* reason for vvp32.
OK, I understand, so for a rpm package
Stephen Williams wrote:
The way you handle that is to create a sub-package that depends on
Icarus Verilog. Users can install your main package without requiring
Icarus Verilog, but if they install the icarus verilog interface, they
will naturally require the Icarus Verilog package.
You
Stephen Williams wrote:
[...]
Try adding ivl_lval_width to the ivl.def file in the main source
directory, then rebuild from the top down. It looks like that got
missed in the big fixup.
If that does it for you, I'll check it into CVS.
Thanks Steve, that works.
Guenter
Hi,
I tried to compile Icarus Verilog snapshot 20060809 under cygwin. I
found a bug report about that setup not to compile correct. Along with
that bug report came the patch pr1541452.patch which is applied to the
source.
When I compile the code I am getting a linker error for the tgt-vvp
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