On 23/04/11 05:42, Andrew Poelstra wrote:
> With the current git HEAD, pcb segfaults as soon as
> you click 'png' in the export list. Can anyone confirm
> this isn't just me?
>
>
> Assuming it is an actual bug, I have filed a report
> and attached a patch at
> https://bugs.launchpad.net/pcb/+bug/7
On 08/02/11 09:20, Markus Hitter wrote:
>
> Am 08.02.2011 um 08:44 schrieb rickman:
>
>> Do you expect these tools to be used to design chips costing far, far
>> over $3 Million just for the mask set?
>
> I'm trying to think 20 years into the future. Especially if it's only a
> matter of allowin
On 16/11/10 15:54, Peter TB Brett wrote:
> On Tuesday 16 Nov 2010 11:09:34 timecop wrote:
>> With TopoR having a freeware version for 2 layers and up to 256 nets
>> (or some other fairly high for 'hobby' use limitation), there's not
>> really any point on bothering improving built in autorouter...
On 07/09/10 18:01, DJ Delorie wrote:
Shall we / I push this? I think it looks good overall.
I desparately need to push out a release to get the LF work
"published" in order to close it out. Maybe I'll do a 1.99za release
just to accomplish those goals, then we can cram in all the new
functio
On 26/04/10 20:28, Link wrote:
> (I'll have to reply on other people's scripts, because I don't know any
> Scheme whatsoever.)
(And by "reply" I mean "rely".)
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On 26/04/10 20:08, John Doty wrote:
> Please remember that "features" and "capabilities" are largely opposed in
> software. I would rather ask for an API that allows me to add my own
> features, rather than a feature that I'd like but would likely get in someone
> else's way.
Actually, I agree
On 26/04/10 17:29, Vanessa Ezekowitz wrote:
> On Mon, 26 Apr 2010 11:25:09 + (UTC)
> Kai-Martin Knaak wrote:
>
>> On Mon, 26 Apr 2010 12:25:59 +0200, Link wrote:
>>
>>> [Adding doackable dialogs like Inkscape are] Just something I thought
>>> would
The "puzzled about the purpose of gschem" thread got me thinking about
ways the workflow might be made more efficient, and one thing I thought
of is the ability to dock the dialogue windows to the main window. In
particular, I would find it helpful if I could dock the "add component"
dialogue and t
On 24/04/10 05:46, al davis wrote:
> On Friday 23 April 2010, Link wrote:
>> Eh?
>>
>
> Suppose you had instead said:
> ===
>> .. I suggest
>> using Eagle through Darwine. In my personal experience,
>> Eagle is a lot better tha
On 22/04/10 16:09, al davis wrote:
> I find it somewhat ironic that "penguindevelopment.org" doesn't
> seem to understand the concept.
Eh? I understand it perfectly well. The thing is, though, that sometimes
it is simply not practical to use FLOSS when you need a feature right
away that simply is
On 22/04/10 07:26, Madhusudan Singh wrote:
>Hello,
>
>I am not new (though a tad rusty) to spice, or the usual design
>process. Years ago, I went through an analog circuit design, followed
>by a VLSI design class that involved the use of H-Spice, Mentor
>Graphics and Cadence so
Huh, so something as innocuous as a copyright symbol can cause a system
lock-up. Who'd-a thunk that.
The problem in question: the file gschem/src/x_dialog.c contains a
unicode symbol, the copyright symbol (©). When `xgettext' is called
during the `make' procedure, it chokes on that symbol because
On 16/12/09 09:57, Goran Mekić wrote:
> Is there a way to recognize what footprint I need for an element other
> then printing them all and comparing it to real element? Let's say
> it's 2200uF polar cap. I know it's RCY*, but how to figure out what's
> *? Thanx!
>
>
You'll remember the most
On 29/11/09 02:22, DJ Delorie wrote:
> Er, how are you planning on making *any* board at home, without a
> laser printer?
>
> For two layer, just do whatever you do for one layer, but on both
> sides. Pre-drill a couple of holes to help you line up the two sides.
>
>
>
On 28/11/09 19:36, DJ Delorie wrote:
>> I've designed a circuit that I'm planning to home-fab, and as such,
>> I've had to design my board using only a single layer.
>
> I do 2 and 4 layers at home, no reason why you can't do a double sided
> board. Are you using sockets for all the ICs, or solder
I've designed a circuit that I'm planning to home-fab, and as such, I've
had to design my board using only a single layer. After about a week or
so of puzzling, I've managed to route it. Unfortunately, it looks like
I'll need a metric craptonne of jumper wire, and I was hoping someone
could hel
On 15/10/09 05:25, Peter Clifton wrote:
> I think it takes a good board to show off the potential benefits of the
> 3D view, so I've made another screen-shot.
>
> The board is by John Bass (jb...@dmsd.com), Copyright 2007 DMS Design.
>
> http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-6.p
On 05/09/09 13:16, Kai-Martin Knaak wrote:
> On Sat, 05 Sep 2009 11:30:09 +0200, Link wrote:
>
>> At the moment all I can think of is
>> duplicating the pins, mirroring them horizontally and overlaying them
>> onto the existing pins so that drawing a net to pin 1 connects t
I'm trying to create a symbol for a 2-column, 7-row header, but with
each pin connected to its opposite pin. It's a bit difficult to explain,
so let me provide a simple ASCII picture. :)
This would be the basic header, with pin numbers in hex:
[1][2]
[3][4]
[5][6]
[7][8]
[9][a]
[b][c]
[d][e]
N
On 27/08/09 13:00, Kai-Martin Knaak wrote:
> On Thu, 27 Aug 2009 12:15:58 +0200, Link wrote:
>
>> Hi,
>>
>> I was wondering if anyone had footprints for some ATX connectors, namely
>> the 4-pin Molex 8981 (AMP MATE-N-LOK) connector (male) and the ATX 20+4
>&
Hi,
I was wondering if anyone had footprints for some ATX connectors, namely
the 4-pin Molex 8981 (AMP MATE-N-LOK) connector (male) and the ATX 20+4
motherboard connector (also male). I'm working on a project that's
powered by an ATX supply, but I can't find footprints for the
connectors. I've
On 24/05/09 15:59, Peter Clifton wrote:
> Just though I'd post this.
>
> The implementation is a little kludgy, but it seems to yield the desired
> behaviour.
>
>
> I've been drawing various control block diagrams with gschem recently,
> using an arrow symbol with two pins to indicate signal flow.
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