gene glick writes:
>> This is the board:
>>
>> http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
>>
>> Any idea if it is a good idea to just ignore these violations?
>>
>
> Blindly ignoring violations is probably not a good idea. Better to
> understand them first.
Well, I
Peter Clifton writes:
> On Fri, 2010-03-26 at 16:00 +0100, Stephan Boettcher wrote:
>> This is the board:
>>
>> http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
>>
>> Any idea if it is a good idea to just ignore these violations?
>
Duncan Drennan writes:
> Double-clicking moves the cursor to the violation.
Yes, absolutely wonderful.
Except, ... it centers the cursor on violating entity, and does not show
the second entity that violates the clearance.
I've got 14 DRC violations left mostly on the power plane, that I can
Kai-Martin Knaak writes:
> Sorry, I should have checked. Their domain is genuinely German:
> http://basista.de
>^^
> BTW, the website just got a redesign. It looks much fancier than last
> week. Their pcb service is high quality,though. Last time I got shorted
> tr
Vanessa Ezekowitz writes:
> On Thu, 25 Feb 2010 14:57:20 -0800
> Dave N6NZ wrote:
>
>>
>> On Feb 25, 2010, at 10:45 AM, DJ Delorie wrote:
>>
>> >
>> > Everything in pcb supports non-90 arcs, except for the ability to
>> > create them. Someone needs to come up with a friendly way to
>> > crea
Stephan Boettcher writes:
> Julian writes:
>
>> Stephan,
>> Yes, you can do it, however you can't use the project file for the
>> process. Here's how:
>>
>> gerbv --export=png --dpi=600 --foreground=#ffff
>> --foreground=#00ff0088
Julian writes:
> Stephan,
> Yes, you can do it, however you can't use the project file for the
> process. Here's how:
>
> gerbv --export=png --dpi=600 --foreground=#ffff
> --foreground=#00ff0088 file1.gbx file2.gbx ...and so on
>
> Hope this helps. Cheers--
Absolutely, thanks! No
Moin,
What I like to do: create an assembly drawing for my new shiny layout.
How: Using gerbv to export a PNG image at 600dpi, with the front copper
in translucent red, front paste in a little stronger red on top, to
better see the pads, the deeper layers in very light colors below, and
the silk
Dan McMahill writes:
> Before switching I was a die hard word user.
Word? Wordstar! My first thesis war written with wordstar, on CP/M2.2.
Then I switched to LaTeX. And how proud I was, when EMTeX run faster on
my new 486DX33 notebook, than the TeX on the VAX at the institute (at
night!), un
Peter Clifton writes:
> On Sun, 2010-02-07 at 13:47 +0100, Florian Teply wrote:
>> Right, that would be the case.
>> I just wonder: if one changed the acceleration letters between translation,
>> say from Ne_w to Ne_u (going from english to german), would it still work?
>> Or
>> has the accele
gene glick writes:
> Do you all use Latex for editing docs, or maybe open office or other?
> I'm getting fed up with the open office bugs and starting to think
> that Latex is a better alternative. Busy compiling Lyx as we speak.
My openoffice use is strictly read-only. For text there is LaTeX
Mark Rages writes:
> These operations all have one thing in common: they let you do
> accurate work based on existing objects, without working on a grid.
>
> You can try them in qcad. apt-get install qcad
:-)
With qcad, I use the grid to place the first object, and then turn it
off.
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Dave N6NZ writes:
> On Dec 27, 2009, at 6:12 PM, gene glick wrote:
>> A schematic represents different things to different people:
>> The technician likes the symbols to closely resemble the physical parts.
>> It makes working on the board easier since he doesn't need data sheets
>> in addit
Link writes:
> Since I'm hand-fabbing this and will probably be drawing the lines
> with a permanent marker, all traces should be at least 35 mil wide and
> have a clearance of 25 mil or greater. I've used that method before;
> it's a bit ugly, but it works - for very simple boards, anyway. The
Bill Gatliff writes:
> Stephan Boettcher wrote:
>> Remotely related to this topic, I had this idea:
>>
>> Often, there are several choices for footprint, model, whatever
>> attribute that need to to chosen at some point in the flow. We have
>> proposals
>>
Remotely related to this topic, I had this idea:
Often, there are several choices for footprint, model, whatever
attribute that need to to chosen at some point in the flow. We have proposals
for a kind of database to support the options.
For a lot of simple applications/flows, an extra databas
Peter Clifton writes:
> On Wed, 2009-11-18 at 09:23 +0100, Stephan Boettcher wrote:
>> Peter Clifton writes:
>>
>> > On Tue, 2009-11-17 at 17:10 -0500, DJ Delorie wrote:
>> >>
>> >> What you want is a four-slot-slotted gate symbol, and a separa
Peter Clifton writes:
> On Tue, 2009-11-17 at 17:10 -0500, DJ Delorie wrote:
>>
>> What you want is a four-slot-slotted gate symbol, and a separate power
>> symbol. The slots permute across {gate 1, gate2} x {A-B inputs, B-A
>> inputs}. I.e. you can use the slotting to switch gates *or* swap t
DJ Delorie writes:
> The file format and internal data formats support it, but there's no
> way other than editing the file to set width and height to different
> values.
I do like that fact that the file format supports more general features.
But in this case I may rather prefer to be able to r
Peter Clifton writes:
>> Thank you for coding!
>
> Thanks for the feedback - it is the fact that I know others are using
> the code which keeps me improving it beyond what I needed last time I
> was designing PCBs.
Currently I do not do any layout work, but I'd like to try the new GL
and 3D work
Dave N6NZ writes:
> Karl Hammar wrote:
>> n...@arrl.net:
>>> Karl Hammar wrote:
Is there a way to organize alternative subparts in a project, e.g.
a cpu-card for one user will have one kind a bus-connector and for
another user another bus-connector, but still maintanable as one
>
Dave N6NZ writes:
> Anyway, 80 engg+tech projects are long behind us. I've seen CPU design
> projects with 350+ engineers and 10's of thousands of sheets of
> schematics. When gEDA can scale to that, it will be a power tool.
Designs of this scale are still done by schematic entry today?
Kai-Martin Knaak writes:
> The fix would have to be applied to each and every affected
> back-end.
May I suggest to study this LWN article for how this kind of problem can
be solved in a future-proof way:
http://lwn.net/Articles/336262/
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Steven Michalske writes:
> pick a small set of some chips you care about. lets say a large
> family of the AVR series.
>
> To the symbol:
> Add a virtual pin attribute
> Add the pin map file attribute.
> pinmap=ATmega16.fpm
> device=ATmega16
> footprint=TQFP44_10
> {
And then o
Josef Wolf writes:
> I'd prefer something more scriptable, since I expect to have _lots_ of
> circuits. But at a first glance, it looks like the ps/eps outputs are
> easy to postprocess.
Try gerbv, with a .gvp file as "script". This allows to order and
color the layers as you like, with transp
Joerg writes:
>>> The topper was a professor at my university who said that soon
>>> everything will be ICs, that transistors and most of that discrete
>>> stuff would go away. I burst into laughter in the auditorium, a bit
>>> embarrassing ...
>>
>> Well, in case you haven't noticed, it's heade
Stefan Salewski writes:
> I have variable capacitors (trimmer) which two pins as symbol, but the
> footprint has three pins, pin 1 and 3 are connected internally.
[...]
> - Make a copy of a true 3 pin footprint and rename pin 3 to 1 (this is
> what I did first.)
>
> - Use the 3 pin footprint, l
Duncan Drennan writes:
> Hmmmfigure out how to code pcbor use vim.hmmm, I'll have
> to think about it ;)
Whenever I needed arcs on my boards that were not 90 deg (mostly board
outlines), the geometry was so difficult that I used gnumeric to code
the arcs, for cut'n paste into the PCB
DJ Delorie writes:
> Anyone done any sd-card designs? Looking for symbols, footprints,
> connector recommendations, schematics, anything I can leech off you :-)
>
> Note: SD, not mini- or micro-SD. Surface mount preferred.
Sorry, only got a mini-SD design.
http://www.ieap.uni-kiel.de/et/peo
DJ Delorie writes:
>> those who hack on the source code: what do you use for debugging and
>> development of the project?
>
> emacs, gdb in xterm.
debugging with: gdb in emacs (optionally in xterm)
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Levente Kovacs writes:
> I would like to print labels. For this I'd generate N times some labels, with
> slight different content. Then I have N *.eps file.
>
> Question. How do I merge them into one A4 postscript page?
I'd try 'pstops', after some tool to merge the N .eps files into
one ps file
Dave N6NZ writes:
> Interesting comment, in that on another list I was just in a discussion
> about 2D drawing tools. I am a fan of QCad. Many people complain about
> the "strange" UI on QCad. But after you climb the considerable learning
> curve, you can absolutely fly with it... because
How about a new application, gbom, similar to gattrib, that allows
entry of a BOM.
gbom would import attributes from a schematic and the engineer could
fill all the remaining fields, with the help of matches in a
database.
gnetlist shall merge the bom with the schematic.
The database defines wh
Ben Jackson <[EMAIL PROTECTED]> writes:
> 1) Change the _/ modes to not create those segments if they're not
> electrically necessary. This is a pretty good fix and you'd only see
> odd behavior if you were in rubberband mode and grabbed the corner to
> move it. It wouldn't count as "connected
Ethan Swint <[EMAIL PROTECTED]> writes:
> I'll have to take a look into constructing a footprint with pads on
> both sides of the board.
That works nicely, I did that for flex connectors.
I had the additional problem that the flex layers were inner layers
of the design, with other components on
When the issue of PCB file format changes and layer types cames up,
here's my list of feature requests, to feed into the discussion:
1. For rigid-flex boards I need multiple outline layers, e.g., rigid,
flex, coverlay.
2. With rigid-flex boards I have a need for multiple pairs of
component layer
DJ Delorie <[EMAIL PROTECTED]> writes:
> There are two options:
>
> option 1: create two gate symbols, one with power leads and one
> without. Both have the same slotting info.
>
> option 2: create one slotted gate symbol with no power info, and a
> second box symbol with just power info. This
DJ Delorie <[EMAIL PROTECTED]> writes:
> Still, the pcb file format is very old and probably due for a
> redesign. I suspect if I ever find time to redo the internal layer
> infrastructure, I might end up changing it for that.
I love the PCB file format, its hackability. I hope, the scope of
th
Stefan Salewski <[EMAIL PROTECTED]> writes:
> a) Minimize parasitic capacitance to any AC ground for all
> of the signal I/O pins. Parasitic capacitance on the output and
> inverting input pins can cause instability—on the noninvert-
> ing input, it can react with the source impedance to cause
>
DJ Delorie <[EMAIL PROTECTED]> writes:
>> This superb answer evades the other half of the question: is there
>> a scripting reference?
>
> The pcb.pdf has an Action Reference, yes.
Thanks, yes, I've got a copy of that on my desk. But somehow I was
assuming that the list of action in there is inco
DJ Delorie <[EMAIL PROTECTED]> writes:
> You can export directly from the command line:
>
> pcb -x gerber $*.pcb
This superb answer evades the other half of the question: is there a
scripting reference?
Stephan
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John Griessen <[EMAIL PROTECTED]> writes:
>> For an ignorant user like myself your fancy scripts are not easily
>> discoverable. Modifying PCB layout files with sed, awk, gnumeric
>> ... are easily discoverable procedures :-)
>
> How did you use gnumeric -- awk some commas into the pcb file cont
Thanks a lot, this may all be very helpful.
I did a hierachical schematic, and an sed one-liner was enough to map
the netlist to the copies of a replicated part of the layout.
The point was, that I made that part embedded in the bigger layout,
then copied it into the buffer and tried to save i
Moin,
I was looking for a way to save the buffer contents into a layout
file, to make copies with changed refdes and then pasted those into
the original design. "Save buffer elements to file" actually saves all
Elements, Vias and Planes from the Buffer, but the resulting file
cannot be read via "
Ben,
Ben Jackson <[EMAIL PROTECTED]> writes:
> There are just a couple places in the polygon code which make the
> clearances for pads that call a 'rounded rect' function that would
> have to be changed.
Thanks for the pointer. I just got a CVS built of PCB going, I will
try to look into this.
DJ Delorie <[EMAIL PROTECTED]> writes:
>> later versions of PCB make the clearance in a plane around a
>> rectangular pad with rounded corners. Is there a way/flag to turn
>> that back to the old behaviour, to get rectangular clearance?
>
> No. See http://www.delorie.com/pcb/notches.html
I reme
Hi,
later versions of PCB make the clearance in a plane around a
rectangular pad with rounded corners. Is there a way/flag to turn
that back to the old behaviour, to get rectangular clearance?
I am using 20080202 from Debian sid.
Cheers
Stephan
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