Bad things:
- your friends may make fun of you for not using the latest programmable
solution ;)
Hey, I think that part is the most cool :)
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On 07/28/2011 05:52 PM, Rob Butts wrote:
This is a dumb question but I'm having a mental block.
I have a 12 volt dc motor that I want to run from the push of
a momentary pushbutton which will run until a limit switch gets hit.
Digikey has a power latching relay PB1088-ND
On 06/24/2011 07:10 AM, myken wrote:
This is strange in my simulation the attached circuit works fine. In
real life it kinda works but the signals are distorted like you can
see. I think that has something to do with the fact we used a pulse
transformer to try the circuit. If we
On 06/22/2011 04:39 PM, Andy Fierman wrote:
Vcc and Vss are still sensitive to load. So if the design requires both
Vss and Vee be equal and opposite, then it needs regulation - zener, for
example.
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On 06/16/2011 02:30 PM, myken wrote:
Hello all,
I would appreciate some expert advice.
Are you trying to make a low current power supply?
I agree with DJ - the unequal loading on + and - cycle will average to
something other than zero (unequal capacitors, unequal diodes, etc) If
Vx must
The schematic should be
as readable as possible.
Clearly you do not work where I do :)
(or as some folks say there you go, making sense again)
Preferred signal direction is left to right,
top to bottom.
Me too, whenever possible.
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Colin D Bennett wrote:
As a rather inexperienced PCB designer, I find that I have to throw
away two or three layouts until I get one that is usable--and still
not entirely satisfactory. I always end up with such a mess of traces
that I know I need better organization and a method to the
Kovacs Levente wrote:
I'm currently designing a power amplifier for the HF (3-30MHz) radio
band.
I am selecting capacitors for the low pass harmonic filter bank at the output.
My question is what kind of capacitors should I use? I apply not more then
100V of say 30MHz maximum.
My best bet is
quick link to Wima tech info:
http://www.wima.de/EN/technicalinformation.htm
One really nice thing about plastic film caps is that they fail open.
Ceramic tends to fail short - which can sometimes ruin your day :)
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yamazakir2 wrote:
Anybody know of a source, other than digikey, that sells prefabbed
prewound SMPS transformers?
Try coilcraft :
http://coilcraft.com/prod_pwr.cfm
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John Luciani wrote:
I am looking for a low profile wire to board connector - either two
contacts 5A per contact or four
contacts 2.5A per contact. I need a temperature rating of at least
110degC (preferable
120degC). UL recognized is required.
Being able to remove the wires would be nice but
Rob Butts wrote:
I asked a question a couple of days ago about soldering small smt
components. Kaimartin posted a video of someone soldering smt
components [1]http://www.youtube.com/watch?v=wQXhny3R7lk In the video
the tip to the soldering iron is a shiny silver and you can see
Has anyone worked with Gilbert Cells? I'm having a lot of trouble with
one from ON Semi, MC1496, formerly Motorola's part, I think.
The thing is configured as a product detector. There's 2 input
frequencies and they both mix down to 5 kHz. That part works well.
But, the chip just happens to
My design creates an outline layer. The rectangle the represents the
outline of my board is about 11 X 11. The drawing area is about 20 X
14. In the fab.gbr layer, there is a note at the very bottom stating
Board outline is the centerline of this 10 mil rectangle - 0,0 to
2,14000 mils.
DJ Delorie wrote:
If you do the outline right, PCB should print Board Outline is the
centerline of this path on the fab layer.
I can peek at your .pcb if you want to send me a copy.
Thanks for the offer! I see what was wrong, though. My outline layer
was labeled Outline. Changing it to all
This seems like a bug - when I place some silkscreen on the component
side (not sure about the solder side) PCB sets a flag found. This
makes the silkscreen show up highlighted.
gene
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Markus Hitter wrote:
Instead I even get DRC errors stating the track and the pad are too
close *sigh*
Maybe your design rules are prohibiting making the connection? You
could try disabling the auto enforce drc clearance - look under the
settings menu selections. If that works out, you may
ElementLine [ ...
is that a typo? The line is incomplete. I deleted, and then loaded the
part onto a layout, which worked out.
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If you are willing, send the .pcb file over. I can take a closer look.
gene
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I hope the attachment comes through. If not, I'll post it somewhere.
I cannot get rid of the jagged diagonal lines on my design. There's
lots of them. The picture shows a couple of examples. I've tried
different grid sizes, line widths, but nothing fixes the problem.
Redrawing them in
If the tracks select as a single piece, it is just a rendering artefact
due to the line not being _exactly_ 45 degrees. The gerber plot might be
better when viewed in High quality mode in gerbv.
PCB, and the lower quality gerbv modes don't render anti-aliased lines,
so this is likely the
here's a video I found that answers a lot of questions -
http://store.curiousinventor.com/guides/Surface_Mount_Soldering/QFN/
(scroll down just a little for the video)
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does anyone have experience with this package? I want to know if they
are hard to work with. The exposed pad underneath is a problem for hand
soldering - but maybe could be left unsoldered for prototypes. Maybe
just place some solder paste under there ? If the pcb pads are long
enough, is it
I am looking for a book that for example describes how a
for/while/repeat/forever and other verilog behavioral constructs are
converted to multiplexors/and gates etc.
For FPGA work, I am unaware of any engine that can synthesize those
constructs.
If you read through the XST manual
DJ Delorie wrote:
Shall we / I push this? I think it looks good overall.
off the top of my head . . .
A) slots in planes (may be already in the process?)
B) square/rectangular holes (e.g. mounting tabs)
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gene glick wrote:
Stefan Salewski wrote:
On Sat, 2010-08-28 at 20:35 -0400, gene glick wrote:
I haven't yet put my finger on what operations cause this, but the
PCB GUI window keeps growing larger than my screen! Anybody know
what gives?
yep, sorry about that -
PCB version 20091103
OS
Stefan Salewski wrote:
Please try this: Select File-Preferences, and then General, and
Alternate window layout to allow smaller horizontal size. And try Put
layout name on the window title bar below.
That is a good work around, thanks!
DJ:
What's your screen resolution?
1280 X 800. I have
kai-martin knaak wrote:
Cory Cross wrote:
I always got bit by pressing the Tab key, it would move the focus to
one of the GUI buttons at the top of the screen and nothing more would
pop up in the status bar. Hard to figure out if you are not expecting
it. Another quick hit to Tab and
Stefan Salewski wrote:
On Sun, 2010-08-29 at 14:57 -0400, gene glick wrote:
PCB version 20091103
OS : linux, slackware V12
GUI: GTK
compiled myself.
Desktop: KDE 3.5
I may try it out with another desktop to see if there's any change.
Additionally, I have to apply a patch during boot to make
DJ Delorie wrote:
Sounds like command-line mode, the : key. Press ENTER to run the
command, or ESC to abort it ?
I've had the very same thing happen to me too. Usually if I 'alt-tab'
to another open window, then 'alt-tab' back. Something along those lines
but I've never spent much time
Stefan Salewski wrote:
On Sat, 2010-08-28 at 20:35 -0400, gene glick wrote:
I haven't yet put my finger on what operations cause this, but the PCB
GUI window keeps growing larger than my screen! Anybody know what
gives? It's not the end of the world, just weird.
gene
May it be useful
I haven't yet put my finger on what operations cause this, but the PCB
GUI window keeps growing larger than my screen! Anybody know what
gives? It's not the end of the world, just weird.
gene
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FYI - maybe by design? But I accidentally named 2 hierarchical blocks
with the same refdes's. gnetlist -g drc2 didn't flag it either as a
warning nor an error. The netlist is worked out correct, nonetheless -
but maybe because I don't have any similarly named components within
each block.
On Thu, Jul 22, 2010 at 8:29 PM, Geoff Swan wrote:
I came across this (
http://www.tentlabs.com/InfoSupport/page35/files/Supply_decoupling.pdf)
some
time ago. I would be interested to hear peoples thoughts as there are
clearly many differing views on correct grounding and supply
decoupling.
I have a hierarchical block with these names:
V7 input power to block
V7_RTN input power to block, return leg
V5 output power from block
V5_RTN output power from block , return leg
within the block, V7_RTN and V5_RTN are connected - in other words, it's
a pass through. At the top
Stephen Ecob wrote:
On Sat, Jun 26, 2010 at 10:33 PM, gene glick carzr...@optonline.net wrote:
can anyone recommend a viewer for these drawings?
I like QCad community edition. DXF is its native format, and it can
edit as well as view.
Thanks, that worked great! BTW, I just noticed
billium wrote:
Hello all,
Has anybody got a footprint for a SD card, not mini or micro.
This has been asked in the past but the person with the required
footprint was on geocities which is now defunkt.
I suppose that was me :)
Try this, if you still need it
can anyone recommend a viewer for these drawings?
gene
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Best method to put a hole in a plane?
I tried the zero width line with clearance of 15 mil which sort of
works, but leaves behind a small 0.1 mil line. It's visible on the gerber.
Basically, I want a power plane (+3.3V) with a small power island in the
middle (+1.2V).
thanks
gene
DJ Delorie wrote:
You can either get the git head PCB which has true hole support, or
draw a C shaped polygon where the two arms touch to make a
pseudo-hole.
Hi DJ,
Yep, that seems to work. How does the git head feature work?
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hey, maybe I should look back at my emails :D I see a bunch of stuff
there about this very thing - doh!
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DJ Delorie wrote:
How does the git head feature work?
I haven't had a chance to play with it yet.
It's ok to do it peace meal, isn't it? Make an island, whatever shape.
The surround it with other rectangles, for example, until there's a
desired gap. My power plane is going to be made up
Hi,
I know we've gone over this before, but I still can't get a decent 45
degree line. I've changed to the ,45 line type instead of -/ type
and have the same problem. Last time I brought this up, I was trying to
attach to an already drawn line segment and right at the connection
point
My 45 degree routes don't always make straight lines. There's a very
slight jog in them. Usually, this happens if the route stopped, and
then I added to it. I don't know if that makes much sense, but if it
does, is there a way to clean that up?
I can post a picture of it, if needed.
gene
John Luciani wrote:
When this happens to me it is caused by not starting
on the end point. Sometimes, especially with 45 deg traces, the end point
can be a little tough to select. Also if you have changed to a
coarser grid it can be more difficult to hit the end point.
(* jcl *)
These
I have an 8-bit flash PROM to connect to a uP. It's the only PROM.
Otherwise the micro data bus is 32-bit wide, and SDRAM lives there. The
PROM has it's own CS, ALE, etc. For a better layout, it would be far
easier to route D0 of the uP to D7 of the PROM. I don't see any reason
not to - just
timecop wrote:
Thats funny, i'd rather HAVE my vias covered with solder mask.
Me too, but there's merit to both ways. I work with a guy who made all
the vias visible, but placed them so badly that stuff shorted to them
all the time - like a metal can from a crystal, *bad*. I had him just
Bob Paddock wrote:
On yet another note, has anyone used metal dome push-button switches?
I have used membrane switches with domes. Check their rated life.
After a few hundred thousand operations some of them collapse and short.
Can happen if you are designing equipment for years of service.
DJ Delorie wrote:
I used a tactile switch and some wooden buttons in my alarm clock...
http://www.delorie.com/electronics/alarmclock/
http://www.delorie.com/electronics/alarmclock/20071007-button-detail.jpg
That is pretty close to what I think would work nice. I'm having zero
luck finding
timecop wrote:
Poor excuse. People soldering those close-up components will not know
where to orient it and have to refer to your assembly drawing.
A colleague recently made a board where with the refdes's under the
parts and called it industry standard practice. Nobody liked hauling
around
Stephan Boettcher wrote:
Stephan Boettcher boettc...@physik.uni-kiel.de writes:
I did not dare to ask for so detailed reviews of this board,
Hi Stephan,
Sorry about that - it's a habit of mine.
Your system sounds interesting. I just skimmed through your description
and will read it in
Stephan Boettcher wrote:
And since I do not have much experience with GHz class opamps, I tend to
put the parts rather too close than too far apart. I do not want an
oscillator there.
Some recent work at my day job involved 400 MHz opamps. These things
require careful layout to keep from
What's your opinion on this? In this application, there are connectors
on the front and rear of the box. I could:
1) Make the board large enough that the connectors are in the correct
positions.
or
2) Make 2 cards, one smaller that fits snuggly against the back, for
example and then a 2nd
Stefan Salewski wrote:
On Sat, 2010-03-27 at 14:18 -0400, gene glick wrote:
What's your opinion on this? In this application, there are connectors
on the front and rear of the box.
When ever possible, I would place connectors on front and one side, this
makes live much easier.
Yep
David Griffith wrote:
On yet another note, has anyone used metal dome push-button switches?
Are you talking about those metal snap domes used in Atari 2600 joysticks?
I have no idea about the Atari. But, for example, here's one vendor :
http://www.snaptron.com/homemainxxzxqma100.cfm
What
This is the board:
http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
Any idea if it is a good idea to just ignore these violations?
Blindly ignoring violations is probably not a good idea. Better to
understand them first.
I hope you don't think I am picking on you,
David MacQuigg wrote:
The alternatives I am considering are install under Mac OS X, or set up
a third machine with a suitable Linux distro. I've been using Cygwin
for all my Unix needs, so I would like to stick with that, if possible.
I also use CentOS (a clone of Redhat) on a remote
So now the question is Who else will pledge money?.
John
You can count me in too.
gene
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How do I stop this - it's making me nuts :)
gene
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Peter Clifton wrote:
Just delete the section, and gschem won't try to override anything. It
will - however, save the position when you close the log window /
gschem, and keep that for next time.
worked great - thanks, Peter!
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Facundo Ferrer wrote:
When I try to check my
circuit with drc or drc2 gnetlist finished with a buffer overflow. I
don't know how to solve this. Also, I tried with spice-sdb but gnetlist
finish with Killed.
Have you tried this:
http://www.geda.seul.org/wiki/geda:faq-gnetlist
John Griessen wrote:
Bob Paddock wrote:
Not sure. I know our CM loves that I put fuducials on the QFN
So these footprint fiducials are outboard of the part so they show in a
vision system as the part is being placed? Do you put silk outline outside
them or some silk circles around each
After a very long time, I am just about ready to send out 3 different
boards for fab. I would appreciate any advice to improve my chances of
success. So far here's what has been done:
1. Run DRC on all PCBs with no issues..
2. Checked schematics.
3. Checked schematic matches layout.
4. In
DJ Delorie wrote:
Print out your surface copper layers and put the parts on the printout
to make sure they match.
that's a really good idea, thanks! It'll delay things some, but yeah,
sounds like the conservative way to go. I'll have to order up a bunch
of parts to make it happen but that's
John Luciani wrote:
Check the gerbers and drill files using gerbv.
I use a script that zips and renames all the files for the fab house.
I take the zip file that is created, unzip it and check those files
with gerbv.
For a system of boards that plug into each I might panelize them
(or certainly fix the message window's focus-stealing, attention
grabbing - behaviour. The same is true of the netlist window when you
press F on a net.)
That one burns me often :D
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As has already been mentioned, the problem will be what happens as the
supply turns on. In theory, as VCC ramps up, the 431 will start to
regulate and so limit its own cathode voltage. If VCC exceeds 36V before the
431 has started drawing current then all bets are off.
Crude but you could try
I did not know what the regulator will be used for.
+12V regulator supplies hi/low side mosfet driver. Positive side is
ground, negative side is -50VDC.
LM317 can replace both TL431 and series transistor.
LM317HV.
seems expensive and only comes in large packages. Nice idea though.
Wojciech Kazubski wrote:
- Anyone use these shunt regulators? I'm wondering about the max voltage.
Or set up your mailer to use a fixed-width font..
Yes, that was it - thanks.
I suspect this TL431 isn't a good device for my app. I have an LM317 to
give me around +12V for bootstap voltage
Anyone use these shunt regulators? I'm wondering about the max voltage.
Data sheet says max cathode-to-anode voltage is 36V. What if VCC = 50
V, as in this cheezy drawing is trying to show. R1 and R2 set the
output voltage at the emitter. R3 limits the current to the cathode
*and* drops
gene glick wrote:
Anyone use these shunt regulators? I'm wondering about the max voltage.
wow, that drawing didn't look very good in my mail client, but if you
cut and paste into kedit it looks reasonable. :)
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Bob Paddock wrote:
Anyone know of a proto-house that will do 0.031 thick boards?
All the usual, automatic robot, players I've looked at only do 0.062
tick boards.
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we're getting a bit more OT, but...
yep :)
\chead{\includegraphics{foo.eps}}
I had tried that already but it wasn't quite what I was looking for.
What worked out nice was placing a table in the header and placing
things exactly where I want them.
gene
I switched to LaTeX 15 years ago and have never looked back. mmm
LaTeX.
it just wasn't working well
for a bunch of reasons (bugs, poor scaling to large documents, poor
multi-author support, poor interaction with cvs or other source control
system,
sounds like you live in my cube
I made a polygon on the top layer, and I want to place a component pad
within the polygon. Is there a way to make it connect without adding a
trace? By default the tool places a clearance gap around the pad - so
it doesn't touch.
gene
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Peter Clifton wrote:
You can set the polygon to be solid, s key, but it does mean it will
short against everything it touches.
I often just use a small solid polygon which shorts against things to
bridge the gap between a pad and a bigger, clearing polygon.
Yep, that works ok. I had to
Ben Jackson wrote:
On Sun, Feb 07, 2010 at 09:18:35AM -0500, gene glick wrote:
I made a polygon on the top layer, and I want to place a component pad
within the polygon. Is there a way to make it connect without adding a
trace? By default the tool places a clearance gap around the pad - so
Peter Clifton wrote:
For 0.01 Ohm sensing, you probably want to attempt at making a kelvin
connection, see http://www.edn.com/article/CA502424.html
Interesting. I'm really not yet convinced on the best trace width - if
it turns out to be larger than the pad size of that 0.1 Ohm resistor,
Do you all use Latex for editing docs, or maybe open office or other?
I'm getting fed up with the open office bugs and starting to think that
Latex is a better alternative. Busy compiling Lyx as we speak.
Just curious if it works out well-
thanks
gene
Dave McGuire wrote:
I use OpenOffice for quick dirty stuff, but LaTeX (with PDF output)
for anything that has to look good. Lyx is pretty nice but those types
of front-ends usually just get in the way.
-Dave
First off, thanks for the input from all.
So you write in a text
uv wrote:
Dear Sirs,
How can I move/rotate the reference designator of component in
PCB 20091103? In the previous versions this feature was made by
same controls like moving any other object on the board.
Thank you
Péter
I've had trouble moving text on the 'other' side of the board. If you
What's the right amount of clearance? Seems like .003 is good, but I
don't know. A google search found one article that said for fine
pitched parts, it's better to have the entire row blocked. That is,
instead of individual clearances around each pad, the soldermask exposes
the entire row
Why does this take so long to complete in PCB2008 and 2009 version,
but is a snap in the git head version?
Also, is it really necessary?
gene
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Michael Kamper wrote:
Hi!
Anyone has a sd-card design including a footprint I could use?
I found an old thread but the link provided there is dead and the
author unfortunately doesn't answer.
Sorry for not ever replying, somehow I missed this. Try this link
instead of the original:
DJ Delorie wrote:
I'm not exactly sure what's best here, but I know it doesn't belong in
the *gate*. My idea is to have a table object that shows up in the
schematic, like in a corner or something, that lists all the power
pins and what nets they connect to. I've seen other schematics
I can create text on the solder side of the board, but cannot move it,
select it, rotate it or delete it. At some point earlier, I placed a
bunch of text on the back side of the board and was able to rotate and
move it. Now I can't.
Any help? PCB version 20081128 (I tried in a newer build
update to that last post:
Method 1 - This sequence leads to the problem:
1. Open PCB
2. Turn off all layers except component side.
3. Flip board (tab)
Method 2 - But, this sequence always seems to work:
1. Open PCB
2. Flip board (tab)
3. Turn off all layers except solder side.
I usually turn
gene glick wrote:
update to that last post:
Method 1 - This sequence leads to the problem:
1. Open PCB
2. Turn off all layers except component side.
3. Flip board (tab)
Method 2 - But, this sequence always seems to work:
1. Open PCB
2. Flip board (tab)
3. Turn off all layers except
DJ Delorie wrote:
Try no grid
Same result :(
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Here's the specs for a radial leaded capacitor:
7.5mm lead spacing, +/- 0.4mm
lead diameter, phi = 0.5mm
What makes more sense for pcb layout:
1) Go with the spec as-is, and squeeze the leads into board if spacing
is off nominal.
2) Use 7.5mm spacing with large holes to accommodate the
I've hit this problem a couple of times now. Any plain text on the
schematic is messing up the backend processing. The most recent problem
occurred when I made a very minor change, rotated a connector on the
schematic. Gnetlist -g PCB reports read garbage and points to the sch
file that I
Anybody have this?
gene
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I'm trying to find some info on the temperature variation of the reverse
saturation current of a diode. Anyone know about this?
gene
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I'm working on something, and a side effect of it outputs the schematic
hierarchy. Is this useful to anyone?
The syntax is '.' is the top-most directory of the schematic. '/'
separates the paths and the schematic name. So, for example,
./schematic1.sch is a schematic located at the root of
Wow - what happened to my last email? OK, here's another attempt . . .
I am working on a program, and it has a side benefit that displays the
schematic hierarchy. Is that something anyone could use?
Here's a sample output:
./ampzilla-base_pg1.sch
./S2/fpga_pg1.sch
./S2/fpga_pg2.sch
sorry for that - somehow my email client went all squirrelly and didn't
display the message content. You can ignore this take 2 version.
gene
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I've tried this in both version 1.4.0 release and 1.5.2, with different
messages, but all fail. I've tried
gnetlist -g partslist
gnetlist -g partslist1
gnetlist -g partslist2
gnetlist -g partslist3
and all fail. Any help?
Here's the output from gnetlist -g partslist1 (partslist2 partslist3
Mark Rages wrote:
I thought the whole point
of a Schmitt input was to give the input a little snap and therefore
increase the rise/fall times.
It will.
In my setup, 2 channels each setup as I described. The relative phase
from one channel to the other remained pretty much constant
The gain is set at -10. The prior stage has gain, and off-hand I don't
recall how large the signal is, I'll check.
GBW for the part is 8MHz, I run it at 5kHz*10= 50 kHz GBW - plenty of
headroom there.
SR definition is SR = 2 * pi * f * Vpk
So I need SR 6.28 * 5000 cycles/sec * 15 Volts, or
Martin Maney wrote:
Nah. You should use a good comparator with controlled hysteresis. An
opamp, any opamp, makes at best a mediocre comparator.
Actually, it worked! Not sure why I didn't think of it earlier, but I
threw the circuit into simulation to see. By cranking the gain up from
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